226 lines
7.6 KiB
Verilog
226 lines
7.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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module control_registers
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(
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//bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack,
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//control
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input [31:0] err_i,
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output [10:0] pwm_open_o,
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output [31:0] reference_speed_o,
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output [31:0] kp_o,
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output [31:0] ki_o,
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output [31:0] kd_o,
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output [31:0] kp1_o,
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output [31:0] ki1_o,
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output [31:0] kd1_o,
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output run_o,
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output break_o,
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output dir_o,
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output star_delta_o,
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output [ 1:0] sensors_o,
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output [ 3:0] gpo_o,
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output oloop_matlab_o,
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output calibrate_adcs_o
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);
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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//internal registers
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reg [31:0] control_r;
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reg [31:0] reference_speed_r;
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reg [31:0] kp_r;
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reg [31:0] ki_r;
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reg [31:0] kp1_r;
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reg [31:0] ki1_r;
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reg [31:0] kd1_r;
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reg [31:0] pwm_open_r;
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reg [31:0] pwm_break_r;
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reg [31:0] status_r;
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reg [31:0] reserved_r1;
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reg [31:0] kd_r;
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reg [10:0] gpo_r;
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//------------------------------------------------------------------------------
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//----------- Wires Declarations -----------------------------------------------
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//------------------------------------------------------------------------------
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wire up_wreq_s;
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wire up_rreq_s;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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assign up_wreq_s = (up_waddr[13:4] == 10'h00) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:4] == 10'h00) ? up_rreq : 1'b0;
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assign run_o = control_r[0]; // Run the motor
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assign break_o = control_r[2]; // Activate the Break circuit
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assign dir_o = control_r[3]; // 0 CCW, 1 CW
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assign star_delta_o = control_r[4]; // Select between star [0] or delta [1] controller
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assign sensors_o = control_r[9:8]; // Select between Hall[00] and BEMF[01] sensors
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assign calibrate_adcs_o = control_r[16];
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assign oloop_matlab_o = control_r[12]; // Select between open loop control [0] and matlab control [1]
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assign gpo_o = control_r[23:20];
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assign pwm_open_o = pwm_open_r[10:0]; // PWM value, for open loop control
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assign reference_speed_o = reference_speed_r;
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assign kp_o = kp_r; // KP controller parameter
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assign ki_o = ki_r; // KI controller parameter
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assign kd_o = kd_r; // KD controller parameter
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assign kp1_o = kp1_r;
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assign kd1_o = kd1_r;
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assign ki1_o = ki1_r;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk)
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begin
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if (up_rstn == 0)
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begin
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reserved_r1 <= 'd0;
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up_wack <= 1'b0;
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control_r <= 'h0;
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reference_speed_r <= 'd1000;
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kp_r <= 'd6554;
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ki_r <= 'd26;
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kd_r <= 'd655360;
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kp1_r <= 'd0;
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ki1_r <= 'd0;
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kd1_r <= 'd0;
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pwm_open_r <= 'h5ff;
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pwm_break_r <= 'd0;
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status_r <= 'd0;
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end
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else
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begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h3))
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begin
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reserved_r1 <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4))
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begin
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control_r <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5))
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begin
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reference_speed_r <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6))
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begin
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kp_r <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h7))
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begin
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ki_r <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8))
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begin
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kd_r <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9))
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begin
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kp1_r <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'ha))
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begin
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ki1_r <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hb))
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begin
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kd1_r <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hc))
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begin
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pwm_open_r <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hd))
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begin
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pwm_break_r <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'he))
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begin
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status_r <= up_wdata;
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk)
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begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end
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else
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begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[3:0])
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4'h3: up_rdata <= reserved_r1;
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4'h4: up_rdata <= control_r;
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4'h5: up_rdata <= reference_speed_r;
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4'h6: up_rdata <= kp_r;
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4'h7: up_rdata <= ki_r;
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4'h8: up_rdata <= kd_r;
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4'h9: up_rdata <= kp1_r;
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4'ha: up_rdata <= ki1_r;
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4'hb: up_rdata <= kd1_r;
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4'hc: up_rdata <= pwm_open_r;
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4'hd: up_rdata <= pwm_break_r;
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4'he: up_rdata <= status_r;
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4'hf: up_rdata <= err_i;
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default: up_rdata <= 0;
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endcase
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end
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else
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begin
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up_rdata <= 32'd0;
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end
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end
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end
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endmodule
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