92 lines
3.6 KiB
Verilog
92 lines
3.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// black box definition for pr module
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`timescale 1ns/100ps
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(* black_box *)
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module prcfg (
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input clk,
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input [31:0] adc_gpio_input,
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output [31:0] adc_gpio_output,
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input [31:0] dac_gpio_input,
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output [31:0] dac_gpio_output,
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input dma_dac_i0_enable,
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output [15:0] dma_dac_i0_data,
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input dma_dac_i0_valid,
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input dma_dac_q0_enable,
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output [15:0] dma_dac_q0_data,
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input dma_dac_q0_valid,
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input dma_dac_i1_enable,
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output [15:0] dma_dac_i1_data,
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input dma_dac_i1_valid,
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input dma_dac_q1_enable,
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output [15:0] dma_dac_q1_data,
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input dma_dac_q1_valid,
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output core_dac_i0_enable,
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input [15:0] core_dac_i0_data,
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output core_dac_i0_valid,
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output core_dac_q0_enable,
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input [15:0] core_dac_q0_data,
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output core_dac_q0_valid,
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output core_dac_i1_enable,
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input [15:0] core_dac_i1_data,
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output core_dac_i1_valid,
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output core_dac_q1_enable,
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input [15:0] core_dac_q1_data,
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output core_dac_q1_valid,
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input dma_adc_i0_enable,
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input [15:0] dma_adc_i0_data,
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input dma_adc_i0_valid,
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input dma_adc_q0_enable,
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input [15:0] dma_adc_q0_data,
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input dma_adc_q0_valid,
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input dma_adc_i1_enable,
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input [15:0] dma_adc_i1_data,
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input dma_adc_i1_valid,
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input dma_adc_q1_enable,
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input [15:0] dma_adc_q1_data,
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input dma_adc_q1_valid,
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output core_adc_i0_enable,
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output [15:0] core_adc_i0_data,
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output core_adc_i0_valid,
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output core_adc_q0_enable,
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output [15:0] core_adc_q0_data,
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output core_adc_q0_valid,
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output core_adc_i1_enable,
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output [15:0] core_adc_i1_data,
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output core_adc_i1_valid,
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output core_adc_q1_enable,
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output [15:0] core_adc_q1_data,
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output core_adc_q1_valid
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);
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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