132 lines
3.9 KiB
Verilog
132 lines
3.9 KiB
Verilog
// ***************************************************************************
|
|
// ***************************************************************************
|
|
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
|
//
|
|
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
|
// A PARTICULAR PURPOSE.
|
|
//
|
|
// Redistribution and use of source or resulting binaries, with or without modification
|
|
// of this file, are permitted under one of the following two license terms:
|
|
//
|
|
// 1. The GNU General Public License version 2 as published by the
|
|
// Free Software Foundation, which can be found in the top level directory of
|
|
// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
|
//
|
|
// OR
|
|
//
|
|
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
|
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
|
// This will allow to generate bit files and not release the source code,
|
|
// as long as it attaches to an ADI device.
|
|
//
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|
|
|
|
`timescale 1ns/100ps
|
|
|
|
module system_top (
|
|
|
|
input [12:0] gpio_bd_i,
|
|
output [ 7:0] gpio_bd_o,
|
|
|
|
input rx_clk_in_p,
|
|
input rx_clk_in_n,
|
|
input rx_frame_in_p,
|
|
input rx_frame_in_n,
|
|
input [ 5:0] rx_data_in_p,
|
|
input [ 5:0] rx_data_in_n,
|
|
output tx_clk_out_p,
|
|
output tx_clk_out_n,
|
|
output tx_frame_out_p,
|
|
output tx_frame_out_n,
|
|
output [ 5:0] tx_data_out_p,
|
|
output [ 5:0] tx_data_out_n,
|
|
|
|
output enable,
|
|
output txnrx,
|
|
|
|
output gpio_resetb,
|
|
output gpio_sync,
|
|
output gpio_en_agc,
|
|
output [ 3:0] gpio_ctl,
|
|
input [ 7:0] gpio_status,
|
|
|
|
output spi_csn,
|
|
output spi_clk,
|
|
output spi_mosi,
|
|
input spi_miso);
|
|
|
|
// internal signals
|
|
|
|
wire [95:0] gpio_i;
|
|
wire [95:0] gpio_o;
|
|
wire [ 2:0] spi0_csn;
|
|
|
|
// defaults
|
|
|
|
assign gpio_resetb = gpio_o[46:46];
|
|
assign gpio_sync = gpio_o[45:45];
|
|
assign gpio_en_agc = gpio_o[44:44];
|
|
assign gpio_ctl = gpio_o[43:40];
|
|
assign gpio_bd_o = gpio_o[20:13];
|
|
|
|
assign gpio_i[95:40] = gpio_o[95:40];
|
|
assign gpio_i[39:32] = gpio_status;
|
|
assign gpio_i[31:13] = gpio_o[31:13];
|
|
assign gpio_i[12: 0] = gpio_bd_i;
|
|
|
|
assign spi_csn = spi0_csn[0];
|
|
|
|
// instantiations
|
|
|
|
system_wrapper i_system_wrapper (
|
|
.enable (enable),
|
|
.gpio_i (gpio_i),
|
|
.gpio_o (gpio_o),
|
|
.ps_intr_00 (1'b0),
|
|
.ps_intr_01 (1'b0),
|
|
.ps_intr_02 (1'b0),
|
|
.ps_intr_03 (1'b0),
|
|
.ps_intr_04 (1'b0),
|
|
.ps_intr_05 (1'b0),
|
|
.ps_intr_06 (1'b0),
|
|
.ps_intr_07 (1'b0),
|
|
.ps_intr_08 (1'b0),
|
|
.ps_intr_09 (1'b0),
|
|
.ps_intr_10 (1'b0),
|
|
.ps_intr_11 (1'b0),
|
|
.ps_intr_14 (1'b0),
|
|
.ps_intr_15 (1'b0),
|
|
.rx_clk_in_n (rx_clk_in_n),
|
|
.rx_clk_in_p (rx_clk_in_p),
|
|
.rx_data_in_n (rx_data_in_n),
|
|
.rx_data_in_p (rx_data_in_p),
|
|
.rx_frame_in_n (rx_frame_in_n),
|
|
.rx_frame_in_p (rx_frame_in_p),
|
|
.spi0_csn (spi0_csn),
|
|
.spi0_miso (spi_miso),
|
|
.spi0_mosi (spi_mosi),
|
|
.spi0_sclk (spi_clk),
|
|
.spi1_csn (),
|
|
.spi1_miso (1'b0),
|
|
.spi1_mosi (),
|
|
.spi1_sclk (),
|
|
.tdd_sync_i (1'b0),
|
|
.tdd_sync_o (),
|
|
.tdd_sync_t (),
|
|
.tx_clk_out_n (tx_clk_out_n),
|
|
.tx_clk_out_p (tx_clk_out_p),
|
|
.tx_data_out_n (tx_data_out_n),
|
|
.tx_data_out_p (tx_data_out_p),
|
|
.tx_frame_out_n (tx_frame_out_n),
|
|
.tx_frame_out_p (tx_frame_out_p),
|
|
.txnrx (txnrx),
|
|
.up_enable (gpio_o[47]),
|
|
.up_txnrx (gpio_o[48]));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|