b7d8e38c94
+ Clean out the code, delete unnecessary flops + Add support for channel count (C_CH_CNT) + FIFO write (data from DMAC/upack) : valid just when xfer_req is asserted, address is free running, new xfer_req resets the address + FIFO read (data to DAC) : free running, reads to max address |
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README.md |
README.md
hdl
Analog Devices HDL libraries and projects
Tools version:
- Vivado 2014.4.1
- Quartus 14.0
First time users, it is highly recommended to go through our HDL user guide at the following url:
http://wiki.analog.com/resources/fpga/docs/hdl
For support please visit our FPGA Reference Designs Support Community on EngineerZone: