18 lines
950 B
Plaintext
18 lines
950 B
Plaintext
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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create_clock -period "4.000 ns" -name ref_clk_250mhz [get_ports {ref_clk}]
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create_clock -period "8.000 ns" -name eth_rx_clk_125mhz [get_ports {eth_rx_clk}]
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derive_pll_clocks
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derive_clock_uncertainty
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set_clock_groups -exclusive \
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-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
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-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
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-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
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set_clock_groups -asynchronous \
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-group {ref_clk_250mhz} \
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-group [get_clocks {i_system_bd|fmcjesdadc1|xcvr_rx_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
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-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]
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