90 lines
3.6 KiB
Verilog
90 lines
3.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2016(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_sysref_gen (
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input core_clk,
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input sysref_en,
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output reg sysref_out
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);
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// SYSREF period is multiple of core_clk, and has a duty cycle of 50%
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// NOTE: if SYSREF always on (this is a JESD204 IP configuration),
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// the period must be a correct multiple of the multiframe period
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parameter SYSREF_PERIOD = 128;
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localparam SYSREF_HALFPERIOD = SYSREF_PERIOD/2 - 1;
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reg [ 7:0] counter;
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reg sysref_en_m1;
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reg sysref_en_m2;
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reg sysref_en_int;
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// bring the enable signal to JESD core clock domain
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always @(posedge core_clk) begin
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sysref_en_m1 <= sysref_en;
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sysref_en_m2 <= sysref_en_m1;
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sysref_en_int <= sysref_en_m2;
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end
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// free running counter for periodic SYSREF generation
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always @(posedge core_clk) begin
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if (sysref_en_int) begin
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counter <= (counter < SYSREF_HALFPERIOD) ? counter + 1 : 0;
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end else begin
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counter <= 0;
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end
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end
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// generate SYSREF
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always @(posedge core_clk) begin
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if (sysref_en_int) begin
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if (counter == SYSREF_HALFPERIOD) begin
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sysref_out <= ~sysref_out;
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end
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end else begin
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sysref_out <= 1'b0;
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end
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end
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endmodule
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