344 lines
10 KiB
Verilog
344 lines
10 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module adrv9001_rx_link #(
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parameter CMOS_LVDS_N = 0
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) (
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input adc_rst,
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input adc_clk_div,
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input [7:0] adc_data_0,
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input [7:0] adc_data_1,
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input [7:0] adc_data_2,
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input [7:0] adc_data_3,
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input [7:0] adc_data_strobe,
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input adc_valid,
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// upper layer data interface
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output rx_clk,
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output rx_data_valid,
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output [15:0] rx_data_i,
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output [15:0] rx_data_q,
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// Config interface
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input rx_sdr_ddr_n,
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input rx_single_lane
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);
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wire [7:0] data_0;
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wire [7:0] data_1;
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wire [7:0] data_2;
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wire [7:0] data_3;
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wire [7:0] data_strobe;
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wire data_valid;
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assign rx_clk = adc_clk_div;
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// CMOS can operate in SDR or DDR mode
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generate if (CMOS_LVDS_N) begin : cmos_4_to_8
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wire [3:0] sdr_data_0;
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wire [3:0] sdr_data_1;
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wire [3:0] sdr_data_2;
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wire [3:0] sdr_data_3;
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wire [3:0] sdr_data_strobe;
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wire sdr_data_valid;
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wire [3:0] sdr_data_0_aligned;
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wire [3:0] sdr_data_1_aligned;
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wire [3:0] sdr_data_2_aligned;
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wire [3:0] sdr_data_3_aligned;
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wire [3:0] sdr_data_strobe_aligned;
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wire [7:0] sdr_data_0_packed;
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wire [7:0] sdr_data_1_packed;
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wire [7:0] sdr_data_2_packed;
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wire [7:0] sdr_data_3_packed;
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wire [7:0] sdr_data_strobe_packed;
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wire aligner4_ovalid;
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// For SDR drop every second DDR bit
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assign sdr_data_0 = {adc_data_0[7],adc_data_0[5],adc_data_0[3],adc_data_0[1]};
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assign sdr_data_1 = {adc_data_1[7],adc_data_1[5],adc_data_1[3],adc_data_1[1]};
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assign sdr_data_2 = {adc_data_2[7],adc_data_2[5],adc_data_2[3],adc_data_2[1]};
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assign sdr_data_3 = {adc_data_3[7],adc_data_3[5],adc_data_3[3],adc_data_3[1]};
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assign sdr_data_strobe = {adc_data_strobe[7],adc_data_strobe[5],adc_data_strobe[3],adc_data_strobe[1]};
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adrv9001_aligner4 i_rx_aligner4_0 (
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.clk (adc_clk_div),
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.rst (adc_rst),
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.idata (sdr_data_0),
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.ivalid (adc_valid),
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.strobe (sdr_data_strobe),
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.odata (sdr_data_0_aligned)
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);
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adrv9001_aligner4 i_rx_aligner4_1 (
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.clk (adc_clk_div),
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.rst (adc_rst),
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.idata (sdr_data_1),
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.ivalid (adc_valid),
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.strobe (sdr_data_strobe),
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.odata (sdr_data_1_aligned)
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);
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adrv9001_aligner4 i_rx_aligner4_2 (
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.clk (adc_clk_div),
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.rst (adc_rst),
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.idata (sdr_data_2),
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.ivalid (adc_valid),
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.strobe (sdr_data_strobe),
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.odata (sdr_data_2_aligned)
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);
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adrv9001_aligner4 i_rx_aligner4_3 (
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.clk (adc_clk_div),
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.rst (adc_rst),
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.idata (sdr_data_3),
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.ivalid (adc_valid),
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.strobe (sdr_data_strobe),
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.odata (sdr_data_3_aligned)
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);
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adrv9001_aligner4 i_rx_aligner4_strobe (
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.clk (adc_clk_div),
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.rst (adc_rst),
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.idata (sdr_data_strobe),
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.ivalid (adc_valid),
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.strobe (sdr_data_strobe),
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.ovalid (aligner4_ovalid),
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.odata (sdr_data_strobe_aligned)
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);
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adrv9001_pack #(
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.WIDTH(4)
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) i_rx_pack_4_to_8_0 (
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.clk (adc_clk_div),
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.rst (adc_rst),
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.idata (sdr_data_0_aligned),
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.ivalid (aligner4_ovalid),
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.sof (sdr_data_strobe_aligned[3]),
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.odata (sdr_data_0_packed),
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.ovalid (sdr_data_valid)
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);
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adrv9001_pack #(
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.WIDTH(4)
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) i_rx_pack_4_to_8_1 (
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.clk (adc_clk_div),
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.rst (adc_rst),
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.idata (sdr_data_1_aligned),
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.ivalid (aligner4_ovalid),
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.sof (sdr_data_strobe_aligned[3]),
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.odata (sdr_data_1_packed),
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.ovalid ()
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);
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adrv9001_pack #(
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.WIDTH(4)
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) i_rx_pack_4_to_8_2 (
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.clk (adc_clk_div),
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.idata (sdr_data_2_aligned),
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.ivalid (aligner4_ovalid),
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.sof (sdr_data_strobe_aligned[3]),
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.odata (sdr_data_2_packed),
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.ovalid ()
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);
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adrv9001_pack #(
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.WIDTH(4)
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) i_rx_pack_4_to_8_3 (
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.clk (adc_clk_div),
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.rst (adc_rst),
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.idata (sdr_data_3_aligned),
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.ivalid (aligner4_ovalid),
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.sof (sdr_data_strobe_aligned[3]),
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.odata (sdr_data_3_packed),
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.ovalid ()
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);
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adrv9001_pack #(
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.WIDTH(4)
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) i_rx_pack_4_to_8_strobe (
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.clk (adc_clk_div),
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.rst (adc_rst),
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.idata (sdr_data_strobe_aligned),
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.ivalid (aligner4_ovalid),
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.sof (sdr_data_strobe_aligned[3]),
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.odata (sdr_data_strobe_packed),
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.ovalid ()
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);
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assign data_0 = rx_sdr_ddr_n ? sdr_data_0_packed : adc_data_0;
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assign data_1 = rx_sdr_ddr_n ? sdr_data_1_packed : adc_data_1;
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assign data_2 = rx_sdr_ddr_n ? sdr_data_2_packed : adc_data_2;
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assign data_3 = rx_sdr_ddr_n ? sdr_data_3_packed : adc_data_3;
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assign data_strobe = rx_sdr_ddr_n ? sdr_data_strobe_packed : adc_data_strobe;
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assign data_valid = rx_sdr_ddr_n ? sdr_data_valid : adc_valid;
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end else begin
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assign data_0 = adc_data_0;
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assign data_1 = adc_data_1;
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assign data_2 = adc_data_2;
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assign data_3 = adc_data_3;
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assign data_strobe = adc_data_strobe;
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assign data_valid = adc_valid;
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end
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endgenerate
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// ADC
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wire [7:0] rx_data8_0_aligned;
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wire [7:0] rx_data8_1_aligned;
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wire [7:0] rx_data8_2_aligned;
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wire [7:0] rx_data8_3_aligned;
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wire [7:0] rx_data8_strobe_aligned;
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wire rx_data8_0_aligned_valid;
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wire rx_data8_1_aligned_valid;
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wire [15:0] rx_data16_0_packed;
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wire [15:0] rx_data16_1_packed;
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wire rx_data16_0_packed_valid;
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wire rx_data16_0_packed_osof;
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wire [31:0] rx_data32_0_packed;
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wire rx_data32_0_packed_valid;
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adrv9001_aligner8 i_rx_aligner8_0(
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.clk (adc_clk_div),
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.rst (adc_rst),
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.idata (data_0),
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.ivalid (data_valid),
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.strobe (data_strobe),
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.odata (rx_data8_0_aligned),
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.ovalid (rx_data8_0_aligned_valid)
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);
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adrv9001_aligner8 i_rx_aligner8_1(
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.clk (adc_clk_div),
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.rst (adc_rst),
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.ivalid (data_valid),
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.idata (data_1),
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.strobe (data_strobe),
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.odata (rx_data8_1_aligned),
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.ovalid (rx_data8_1_aligned_valid)
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);
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generate if (CMOS_LVDS_N) begin : cmos_aligner8
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adrv9001_aligner8 i_rx_aligner8_2(
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.clk (adc_clk_div),
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.rst (adc_rst),
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.idata (data_2),
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.ivalid (data_valid),
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.strobe (data_strobe),
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.odata (rx_data8_2_aligned)
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);
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adrv9001_aligner8 i_rx_aligner8_3(
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.clk (adc_clk_div),
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.rst (adc_rst),
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.idata (data_3),
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.ivalid (data_valid),
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.strobe (data_strobe),
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.odata (rx_data8_3_aligned)
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);
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end
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endgenerate
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adrv9001_aligner8 i_rx_strobe_aligner(
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.clk (adc_clk_div),
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.rst (adc_rst),
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.idata (data_strobe),
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.ivalid (data_valid),
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.strobe (data_strobe),
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.odata (rx_data8_strobe_aligned)
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);
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adrv9001_pack #(
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.WIDTH (8)
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) i_rx_pack_8_to_16_0 (
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.clk (adc_clk_div),
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.rst (adc_rst),
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.ivalid (rx_data8_0_aligned_valid),
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.idata (rx_data8_0_aligned),
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.sof (rx_data8_strobe_aligned[7]),
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.odata (rx_data16_0_packed),
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.ovalid (rx_data16_0_packed_valid),
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.osof (rx_data16_0_packed_osof)
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);
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adrv9001_pack #(
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.WIDTH (8)
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) i_rx_pack_8_to_16_1 (
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.clk (adc_clk_div),
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.rst (adc_rst),
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.ivalid (rx_data8_1_aligned_valid),
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.idata (rx_data8_1_aligned),
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.sof (rx_data8_strobe_aligned[7]),
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.odata (rx_data16_1_packed),
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.ovalid ()
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);
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adrv9001_pack #(
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.WIDTH (16)
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) i_rx_pack_16_to_32_0 (
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.clk (adc_clk_div),
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.rst (adc_rst),
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.ivalid (rx_data16_0_packed_valid),
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.idata (rx_data16_0_packed),
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.sof (rx_data16_0_packed_osof),
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.odata (rx_data32_0_packed),
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.ovalid (rx_data32_0_packed_valid)
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);
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generate if (CMOS_LVDS_N) begin
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assign rx_data_i = ~rx_single_lane ? {rx_data8_1_aligned,rx_data8_0_aligned} :
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rx_data32_0_packed[31:16];
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assign rx_data_q = ~rx_single_lane ? {rx_data8_3_aligned,rx_data8_2_aligned} :
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rx_data32_0_packed[15:0];
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assign rx_data_valid = ~rx_single_lane ? rx_data8_0_aligned_valid :
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rx_data32_0_packed_valid;
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end else begin
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assign rx_data_i = ~rx_single_lane ? rx_data16_0_packed :
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rx_data32_0_packed[31:16];
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assign rx_data_q = ~rx_single_lane ? rx_data16_1_packed :
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rx_data32_0_packed[15:0];
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assign rx_data_valid = ~rx_single_lane ? rx_data16_0_packed_valid :
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rx_data32_0_packed_valid;
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end
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endgenerate
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endmodule
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