84 lines
2.4 KiB
Tcl
84 lines
2.4 KiB
Tcl
###############################################################################
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## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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package require qsys 14.0
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package require quartus::device
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
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set_module_property NAME axi_adxcvr
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set_module_property DESCRIPTION "AXI ADXCVR Core"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME axi_adxcvr
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set_module_property ELABORATION_CALLBACK p_axi_adxcvr
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set_module_property VALIDATION_CALLBACK info_param_validate
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# files
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ad_ip_files axi_adxcvr [list \
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$ad_hdl_dir/library/common/up_axi.v \
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axi_adxcvr_up.v \
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axi_adxcvr.v \
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]
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# parameters
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add_parameter ID INTEGER 0
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set_parameter_property ID DISPLAY_NAME ID
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set_parameter_property ID UNITS None
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set_parameter_property ID HDL_PARAMETER true
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add_parameter TX_OR_RX_N INTEGER 0
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set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N
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set_parameter_property TX_OR_RX_N UNITS None
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set_parameter_property TX_OR_RX_N HDL_PARAMETER true
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add_parameter NUM_OF_LANES INTEGER 4
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set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
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set_parameter_property NUM_OF_LANES UNITS None
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set_parameter_property NUM_OF_LANES HDL_PARAMETER true
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adi_add_auto_fpga_spec_params
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adi_add_device_spec_param XCVR_TYPE
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adi_add_device_spec_param FPGA_VOLTAGE
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set_parameter_property FPGA_VOLTAGE DISPLAY_UNITS mV
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set_parameter_property FPGA_VOLTAGE_MANUAL DISPLAY_UNITS mV
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adi_add_indep_spec_params_overwrite XCVR_TYPE
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adi_add_indep_spec_params_overwrite FPGA_VOLTAGE
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# axi4 slave interface
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ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
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# xcvr interface
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ad_interface reset up_rst output 1 s_axi_clock
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set_interface_property if_up_rst associatedResetSinks s_axi_reset
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add_interface core_pll_locked conduit end
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add_interface_port core_pll_locked up_pll_locked pll_locked Input 1
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# name changes
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proc p_axi_adxcvr {} {
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set m_tx_or_rx_n [get_parameter_value TX_OR_RX_N]
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set m_num_of_lanes [get_parameter_value NUM_OF_LANES]
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if {$m_tx_or_rx_n == 1} {
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add_interface ready conduit end
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add_interface_port ready up_ready tx_ready input $m_num_of_lanes
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}
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if {$m_tx_or_rx_n == 0} {
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add_interface ready conduit end
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add_interface_port ready up_ready rx_ready input $m_num_of_lanes
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}
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}
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