220 lines
7.0 KiB
Verilog
220 lines
7.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_xcvrlb #(
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// parameters
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parameter integer CPLL_FBDIV = 1,
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parameter integer CPLL_FBDIV_4_5 = 5,
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parameter NUM_OF_LANES = 1,
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parameter integer XCVR_TYPE = 2
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) (
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// transceiver interface
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input ref_clk,
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input [(NUM_OF_LANES-1):0] rx_p,
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input [(NUM_OF_LANES-1):0] rx_n,
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output [(NUM_OF_LANES-1):0] tx_p,
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output [(NUM_OF_LANES-1):0] tx_n,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready
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);
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// internal registers
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reg up_wack = 'd0;
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reg [31:0] up_scratch = 'd0;
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reg up_resetn = 'd0;
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reg [31:0] up_status = 'd0;
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reg [31:0] up_pll_locked = 'd0;
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reg up_rack = 'd0;
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reg [31:0] up_rdata = 'd0;
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// internal signals
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wire up_rstn;
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wire up_clk;
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wire up_wreq_s;
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wire [ 7:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_rreq_s;
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wire [ 7:0] up_raddr_s;
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wire [31:0] up_status_s;
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wire [31:0] up_pll_locked_s;
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// parameters
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localparam [31:0] VERSION = 32'h00100161;
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// defaults
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assign up_rstn = s_axi_aresetn;
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assign up_clk = s_axi_aclk;
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assign up_status_s[31:NUM_OF_LANES] = 'd0;
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assign up_pll_locked_s[31:NUM_OF_LANES] = 'd0;
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// register access
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_scratch <= 'd0;
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up_resetn <= 'd0;
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up_status <= 'd0;
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up_pll_locked <= 'd0;
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end else begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin
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up_scratch <= up_wdata_s;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h04)) begin
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up_resetn <= up_wdata_s[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h05)) begin
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up_status <= up_status_s | (up_status & ~up_wdata_s);
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end else begin
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up_status <= up_status_s | up_status;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h06)) begin
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up_pll_locked <= up_pll_locked_s | (up_pll_locked & ~up_wdata_s);
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end else begin
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up_pll_locked <= up_pll_locked_s | up_pll_locked;
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end
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end
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end
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr_s)
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10'h000: up_rdata <= VERSION;
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10'h002: up_rdata <= up_scratch;
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10'h004: up_rdata <= {31'd0, up_resetn};
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10'h005: up_rdata <= up_status;
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10'h006: up_rdata <= up_pll_locked;
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default: up_rdata <= 32'd0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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// instantiations
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genvar n;
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generate
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for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lanes
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axi_xcvrlb_1 #(
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.XCVR_TYPE (XCVR_TYPE),
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.CPLL_FBDIV_4_5(CPLL_FBDIV_4_5),
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.CPLL_FBDIV(CPLL_FBDIV)
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) i_xcvrlb_1 (
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.ref_clk (ref_clk),
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.rx_p (rx_p[n]),
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.rx_n (rx_n[n]),
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.tx_p (tx_p[n]),
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.tx_n (tx_n[n]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_resetn (up_resetn),
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.up_status (up_status_s[n]),
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.up_pll_locked (up_pll_locked_s[n]));
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end
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endgenerate
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up_axi #(
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.AXI_ADDRESS_WIDTH (10)
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) i_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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