249 lines
11 KiB
VHDL
249 lines
11 KiB
VHDL
----------------------------------------------------------------------
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---- ----
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---- WISHBONE SPDIF IP Core ----
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---- ----
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---- This file is part of the SPDIF project ----
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---- http://www.opencores.org/cores/spdif_interface/ ----
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---- ----
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---- Description ----
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---- SPDIF receiver component package. ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Geir Drange, gedra@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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--
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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-- Revision 1.8 2004/06/27 16:16:55 gedra
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-- Signal renaming and bug fix.
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--
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-- Revision 1.7 2004/06/26 14:14:47 gedra
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-- Converted to numeric_std and fixed a few bugs.
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--
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-- Revision 1.6 2004/06/23 18:10:17 gedra
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-- Added Wishbone bus cycle decoder.
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--
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-- Revision 1.5 2004/06/16 19:03:45 gedra
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-- Changed status reg. declaration
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--
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-- Revision 1.4 2004/06/13 18:08:09 gedra
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-- Added frame decoder and sample extractor
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--
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-- Revision 1.3 2004/06/10 18:57:36 gedra
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-- Cleaned up lint warnings.
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--
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-- Revision 1.2 2004/06/09 19:24:50 gedra
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-- Added dual port ram.
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--
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-- Revision 1.1 2004/06/07 18:06:00 gedra
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-- Receiver component declarations.
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--
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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package rx_package is
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-- type declarations
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type bus_array is array (0 to 7) of std_logic_vector(31 downto 0);
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-- components
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component rx_ver_reg
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generic (DATA_WIDTH: integer := 32;
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ADDR_WIDTH: integer := 8;
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CH_ST_CAPTURE: integer := 1);
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port (
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ver_rd: in std_logic; -- version register read
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ver_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- read data
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end component;
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component gen_control_reg
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generic (DATA_WIDTH: integer;
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-- note that this vector is (0 to xx), reverse order
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ACTIVE_BIT_MASK: std_logic_vector);
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port (
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clk: in std_logic; -- clock
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rst: in std_logic; -- reset
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ctrl_wr: in std_logic; -- control register write
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ctrl_rd: in std_logic; -- control register read
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ctrl_din: in std_logic_vector(DATA_WIDTH - 1 downto 0);
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ctrl_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0);
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ctrl_bits: out std_logic_vector(DATA_WIDTH - 1 downto 0));
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end component;
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component rx_status_reg
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generic (DATA_WIDTH: integer := 32);
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port (
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up_clk: in std_logic; -- clock
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status_rd: in std_logic; -- status register read
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lock: in std_logic; -- signal lock status
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chas: in std_logic; -- channel A or B select
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rx_block_start: in std_logic; -- start of block signal
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ch_data: in std_logic; -- channel status/user data
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cs_a_en: in std_logic; -- channel status ch. A enable
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cs_b_en: in std_logic; -- channel status ch. B enable
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status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
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end component;
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component gen_event_reg
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generic (DATA_WIDTH: integer := 32);
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port (
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clk: in std_logic; -- clock
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rst: in std_logic; -- reset
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evt_wr: in std_logic; -- event register write
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evt_rd: in std_logic; -- event register read
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evt_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
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event: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector
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evt_mask: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask
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evt_en: in std_logic; -- irq enable
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evt_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data
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evt_irq: out std_logic); -- interrupt request
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end component;
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component rx_cap_reg
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port (
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clk: in std_logic; -- clock
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rst: in std_logic; -- reset
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--cap_ctrl_wr: in std_logic; -- control register write
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--cap_ctrl_rd: in std_logic; -- control register read
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--cap_data_rd: in std_logic; -- data register read
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cap_reg: in std_logic_vector(31 downto 0);
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cap_din: in std_logic_vector(31 downto 0); -- write data
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rx_block_start: in std_logic; -- start of block signal
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ch_data: in std_logic; -- channel status/user data
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ud_a_en: in std_logic; -- user data ch. A enable
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ud_b_en: in std_logic; -- user data ch. B enable
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cs_a_en: in std_logic; -- channel status ch. A enable
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cs_b_en: in std_logic; -- channel status ch. B enable
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cap_dout: out std_logic_vector(31 downto 0); -- read data
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cap_evt: out std_logic); -- capture event (interrupt)
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end component;
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component rx_phase_det
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generic (AXI_FREQ: natural := 33); -- WishBone frequency in MHz
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port (
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up_clk: in std_logic;
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rxen: in std_logic;
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spdif: in std_logic;
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lock: out std_logic;
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lock_evt: out std_logic; -- lock status change event
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rx_data: out std_logic;
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rx_data_en: out std_logic;
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rx_block_start: out std_logic;
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rx_frame_start: out std_logic;
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rx_channel_a: out std_logic;
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rx_error: out std_logic;
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ud_a_en: out std_logic; -- user data ch. A enable
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ud_b_en: out std_logic; -- user data ch. B enable
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cs_a_en: out std_logic; -- channel status ch. A enable
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cs_b_en: out std_logic); -- channel status ch. B enable);
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end component;
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component dpram
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generic (DATA_WIDTH: positive := 32;
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RAM_WIDTH: positive := 8);
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port (
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clk: in std_logic;
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rst: in std_logic; -- reset is optional, not used here
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din: in std_logic_vector(DATA_WIDTH - 1 downto 0);
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wr_en: in std_logic;
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rd_en: in std_logic;
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wr_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);
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rd_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);
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dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
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end component;
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component rx_decode
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generic (DATA_WIDTH: integer range 16 to 32 := 32;
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ADDR_WIDTH: integer range 8 to 64 := 8);
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port (
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up_clk: in std_logic;
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conf_rxen: in std_logic;
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conf_sample: in std_logic;
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conf_valid: in std_logic;
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conf_mode: in std_logic_vector(3 downto 0);
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conf_blken: in std_logic;
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conf_valen: in std_logic;
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conf_useren: in std_logic;
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conf_staten: in std_logic;
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conf_paren: in std_logic;
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lock: in std_logic;
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rx_data: in std_logic;
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rx_data_en: in std_logic;
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rx_block_start: in std_logic;
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rx_frame_start: in std_logic;
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rx_channel_a: in std_logic;
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wr_en: out std_logic;
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wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
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wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0);
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stat_paritya: out std_logic;
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stat_parityb: out std_logic;
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stat_lsbf: out std_logic;
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stat_hsbf: out std_logic);
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end component;
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component rx_wb_decoder
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generic (DATA_WIDTH: integer := 32;
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ADDR_WIDTH: integer := 8);
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port (
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up_clk: in std_logic; -- wishbone clock
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wb_rst_i: in std_logic; -- reset signal
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wb_sel_i: in std_logic; -- select input
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wb_stb_i: in std_logic; -- strobe input
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wb_we_i: in std_logic; -- write enable
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wb_cyc_i: in std_logic; -- cycle input
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wb_bte_i: in std_logic_vector(1 downto 0); -- burts type extension
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wb_adr_i: in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address
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wb_cti_i: in std_logic_vector(2 downto 0); -- cycle type identifier
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data_out: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus
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wb_ack_o: out std_logic; -- acknowledge
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wb_dat_o: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out
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version_rd: out std_logic; -- Version register read
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config_rd: out std_logic; -- Config register read
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config_wr: out std_logic; -- Config register write
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status_rd: out std_logic; -- Status register read
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intmask_rd: out std_logic; -- Interrupt mask register read
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intmask_wr: out std_logic; -- Interrupt mask register write
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intstat_rd: out std_logic; -- Interrupt status register read
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intstat_wr: out std_logic; -- Interrupt status register read
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mem_rd: out std_logic; -- Sample memory read
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mem_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- memory addr.
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ch_st_cap_rd: out std_logic_vector(7 downto 0); -- Ch. status cap. read
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ch_st_cap_wr: out std_logic_vector(7 downto 0); -- Ch. status cap. write
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ch_st_data_rd: out std_logic_vector(7 downto 0)); -- Ch. status data read
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end component;
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end rx_package;
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