479 lines
12 KiB
Verilog
Executable File
479 lines
12 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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DDR_addr,
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DDR_ba,
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DDR_cas_n,
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DDR_ck_n,
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DDR_ck_p,
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DDR_cke,
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DDR_cs_n,
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DDR_dm,
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DDR_dq,
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DDR_dqs_n,
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DDR_dqs_p,
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DDR_odt,
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DDR_ras_n,
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DDR_reset_n,
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DDR_we_n,
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FIXED_IO_ddr_vrn,
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FIXED_IO_ddr_vrp,
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FIXED_IO_mio,
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FIXED_IO_ps_clk,
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FIXED_IO_ps_porb,
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FIXED_IO_ps_srstb,
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gpio_bd,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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spdif,
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iic_scl,
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iic_sda,
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rx_ref_clk_p,
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rx_ref_clk_n,
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rx_sysref_p,
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rx_sysref_n,
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rx_sync_p,
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rx_sync_n,
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rx_data_p,
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rx_data_n,
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spi_fout_enb_clk,
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spi_fout_enb_mlo,
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spi_fout_enb_rst,
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spi_fout_enb_sync,
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spi_fout_enb_sysref,
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spi_fout_enb_trig,
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spi_fout_clk,
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spi_fout_sdio,
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spi_afe_csn,
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spi_afe_clk,
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spi_afe_sdio,
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spi_clk_csn,
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spi_clk_clk,
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spi_clk_sdio,
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afe_mlo_p,
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afe_mlo_n,
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afe_rst_p,
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afe_rst_n,
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afe_trig_p,
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afe_trig_n,
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dac_sleep,
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dac_data,
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afe_pdn,
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afe_stby,
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clk_resetn,
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clk_syncn,
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clk_status,
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amp_disbn,
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prc_sck,
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prc_cnv,
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prc_sdo_i,
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prc_sdo_q);
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inout [14:0] DDR_addr;
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inout [ 2:0] DDR_ba;
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inout DDR_cas_n;
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inout DDR_ck_n;
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inout DDR_ck_p;
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inout DDR_cke;
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inout DDR_cs_n;
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inout [ 3:0] DDR_dm;
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inout [31:0] DDR_dq;
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inout [ 3:0] DDR_dqs_n;
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inout [ 3:0] DDR_dqs_p;
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inout DDR_odt;
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inout DDR_ras_n;
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inout DDR_reset_n;
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inout DDR_we_n;
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inout FIXED_IO_ddr_vrn;
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inout FIXED_IO_ddr_vrp;
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inout [53:0] FIXED_IO_mio;
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inout FIXED_IO_ps_clk;
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inout FIXED_IO_ps_porb;
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inout FIXED_IO_ps_srstb;
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inout [14:0] gpio_bd;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [23:0] hdmi_data;
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output spdif;
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inout iic_scl;
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inout iic_sda;
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input rx_ref_clk_p;
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input rx_ref_clk_n;
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output rx_sysref_p;
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output rx_sysref_n;
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output rx_sync_p;
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output rx_sync_n;
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input [ 7:0] rx_data_p;
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input [ 7:0] rx_data_n;
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output spi_fout_enb_clk;
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output spi_fout_enb_mlo;
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output spi_fout_enb_rst;
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output spi_fout_enb_sync;
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output spi_fout_enb_sysref;
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output spi_fout_enb_trig;
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output spi_fout_clk;
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inout spi_fout_sdio;
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output [ 3:0] spi_afe_csn;
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output spi_afe_clk;
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inout spi_afe_sdio;
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output spi_clk_csn;
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output spi_clk_clk;
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inout spi_clk_sdio;
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output afe_mlo_p;
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output afe_mlo_n;
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output afe_rst_p;
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output afe_rst_n;
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output afe_trig_p;
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output afe_trig_n;
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inout dac_sleep;
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inout [13:0] dac_data;
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inout afe_pdn;
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inout afe_stby;
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inout clk_resetn;
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inout clk_syncn;
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inout clk_status;
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inout amp_disbn;
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inout prc_sck;
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inout prc_cnv;
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inout prc_sdo_i;
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inout prc_sdo_q;
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// internal signals
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wire [10:0] spi_csn;
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wire spi_clk;
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wire spi_mosi;
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wire spi_miso;
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wire rx_ref_clk;
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wire rx_sysref;
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wire rx_sync;
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wire [511:0] adc_ddata;
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wire [127:0] adc_ddata_0;
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wire [127:0] adc_ddata_1;
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wire [127:0] adc_ddata_2;
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wire [127:0] adc_ddata_3;
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wire adc_dovf;
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wire adc_dovf_0;
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wire adc_dovf_1;
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wire adc_dovf_2;
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wire adc_dovf_3;
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wire adc_dsync;
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wire adc_dsync_0;
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wire adc_dsync_1;
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wire adc_dsync_2;
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wire adc_dsync_3;
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wire adc_dwr;
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wire adc_dwr_0;
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wire adc_dwr_1;
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wire adc_dwr_2;
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wire adc_dwr_3;
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wire [255:0] gt_rx_data;
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wire [63:0] gt_rx_data_0;
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wire [63:0] gt_rx_data_1;
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wire [63:0] gt_rx_data_2;
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wire [63:0] gt_rx_data_3;
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wire [43:0] gpio_i;
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wire [43:0] gpio_o;
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wire [43:0] gpio_t;
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wire afe_mlo;
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// spi assignments
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assign spi_fout_enb_clk = spi_csn[10:10];
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assign spi_fout_enb_mlo = spi_csn[ 9: 9];
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assign spi_fout_enb_rst = spi_csn[ 8: 8];
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assign spi_fout_enb_sync = spi_csn[ 7: 7];
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assign spi_fout_enb_sysref = spi_csn[ 6: 6];
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assign spi_fout_enb_trig = spi_csn[ 5: 5];
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assign spi_afe_csn = spi_csn[ 4: 1];
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assign spi_clk_csn = spi_csn[ 0: 0];
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assign spi_fout_clk = spi_clk;
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assign spi_afe_clk = spi_clk;
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assign spi_clk_clk = spi_clk;
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usdrx1_spi i_spi (
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.spi_fout_csn (spi_csn[10:5]),
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.spi_afe_csn (spi_csn[4:1]),
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.spi_clk_csn (spi_csn[0]),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_fout_sdio (spi_fout_sdio),
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.spi_afe_sdio (spi_afe_sdio),
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.spi_clk_sdio (spi_clk_sdio));
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// single dma for all channels
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assign gt_rx_data_3 = gt_rx_data[255:192];
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assign gt_rx_data_2 = gt_rx_data[191:128];
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assign gt_rx_data_1 = gt_rx_data[127: 64];
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assign gt_rx_data_0 = gt_rx_data[ 63: 0];
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assign adc_dwr = adc_dwr_3 | adc_dwr_2 | adc_dwr_1 | adc_dwr_0;
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assign adc_dsync = adc_dsync_3 | adc_dsync_2 | adc_dsync_1 | adc_dsync_0;
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assign adc_ddata = {adc_ddata_3, adc_ddata_2, adc_ddata_1, adc_ddata_0};
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assign adc_dovf_0 = adc_dovf;
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assign adc_dovf_1 = adc_dovf;
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assign adc_dovf_2 = adc_dovf;
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assign adc_dovf_3 = adc_dovf;
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// data interface
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IBUFDS_GTE2 i_ibufds_rx_ref_clk (
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.CEB (1'd0),
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.I (rx_ref_clk_p),
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.IB (rx_ref_clk_n),
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.O (rx_ref_clk),
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.ODIV2 ());
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OBUFDS i_obufds_rx_sysref (
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.I (rx_sysref),
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.O (rx_sysref_p),
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.OB (rx_sysref_n));
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OBUFDS i_obufds_rx_sync (
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.I (rx_sync),
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.O (rx_sync_p),
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.OB (rx_sync_n));
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// gpio/control interface
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OBUFDS i_obufds_mlo (
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.I (afe_mlo),
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.O (afe_mlo_p),
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.OB (afe_mlo_n));
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IOBUF i_iobuf_gpio_prc_sdo_q (
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.I (gpio_o[43]),
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.O (gpio_i[43]),
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.T (gpio_t[43]),
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.IO (prc_sdo_q));
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IOBUF i_iobuf_gpio_prc_sdo_i (
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.I (gpio_o[42]),
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.O (gpio_i[42]),
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.T (gpio_t[42]),
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.IO (prc_sdo_i));
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IOBUF i_iobuf_gpio_prc_cnv (
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.I (gpio_o[41]),
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.O (gpio_i[41]),
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.T (gpio_t[41]),
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.IO (prc_cnv));
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IOBUF i_iobuf_gpio_prc_sck (
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.I (gpio_o[40]),
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.O (gpio_i[40]),
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.T (gpio_t[40]),
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.IO (prc_sck));
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IOBUF i_iobuf_gpio_amp_disbn (
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.I (gpio_o[39]),
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.O (gpio_i[39]),
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.T (gpio_t[39]),
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.IO (amp_disbn));
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IOBUF i_iobuf_gpio_clk_status (
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.I (gpio_o[38]),
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.O (gpio_i[38]),
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.T (gpio_t[38]),
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.IO (clk_status));
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IOBUF i_iobuf_gpio_clk_syncn (
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.I (gpio_o[37]),
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.O (gpio_i[37]),
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.T (gpio_t[37]),
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.IO (clk_syncn));
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IOBUF i_iobuf_gpio_clk_resetn (
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.I (gpio_o[36]),
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.O (gpio_i[36]),
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.T (gpio_t[36]),
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.IO (clk_resetn));
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IOBUF i_iobuf_gpio_afe_stby (
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.I (gpio_o[35]),
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.O (gpio_i[35]),
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.T (gpio_t[35]),
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.IO (afe_stby));
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IOBUF i_iobuf_gpio_afe_pdn (
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.I (gpio_o[34]),
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.O (gpio_i[34]),
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.T (gpio_t[34]),
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.IO (afe_pdn));
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OBUFDS i_obufds_gpio_afe_trig (
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.I (gpio_o[33]),
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.O (afe_trig_p),
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.OB (afe_trig_n));
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OBUFDS i_obufds_gpio_afe_rst (
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.I (gpio_o[32]),
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.O (afe_rst_p),
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.OB (afe_rst_n));
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IOBUF i_iobuf_gpio_dac_sleep (
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.I (gpio_o[30]),
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.O (gpio_i[30]),
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.T (gpio_t[30]),
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.IO (dac_sleep));
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genvar n;
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generate
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for (n = 0; n <= 13; n = n + 1) begin: g_iobuf_gpio_dac_data
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IOBUF i_iobuf_gpio_dac_data (
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.I (gpio_o[16+n]),
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.O (gpio_i[16+n]),
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.T (gpio_t[16+n]),
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.IO (dac_data[n]));
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end
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for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd
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IOBUF i_iobuf_gpio_bd (
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.I (gpio_o[n]),
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.O (gpio_i[n]),
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.T (gpio_t[n]),
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.IO (gpio_bd[n]));
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end
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endgenerate
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system_wrapper i_system_wrapper (
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.DDR_addr (DDR_addr),
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.DDR_ba (DDR_ba),
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.DDR_cas_n (DDR_cas_n),
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.DDR_ck_n (DDR_ck_n),
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.DDR_ck_p (DDR_ck_p),
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.DDR_cke (DDR_cke),
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.DDR_cs_n (DDR_cs_n),
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.DDR_dm (DDR_dm),
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.DDR_dq (DDR_dq),
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.DDR_dqs_n (DDR_dqs_n),
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.DDR_dqs_p (DDR_dqs_p),
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.DDR_odt (DDR_odt),
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.DDR_ras_n (DDR_ras_n),
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.DDR_reset_n (DDR_reset_n),
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.DDR_we_n (DDR_we_n),
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.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
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.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
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.FIXED_IO_mio (FIXED_IO_mio),
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.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
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.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
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.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
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.GPIO_I (gpio_i),
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.GPIO_O (gpio_o),
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.GPIO_T (gpio_t),
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.adc_ddata (adc_ddata),
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.adc_ddata_0 (adc_ddata_0),
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.adc_ddata_1 (adc_ddata_1),
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.adc_ddata_2 (adc_ddata_2),
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.adc_ddata_3 (adc_ddata_3),
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.adc_dovf (adc_dovf),
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.adc_dovf_0 (adc_dovf_0),
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.adc_dovf_1 (adc_dovf_1),
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.adc_dovf_2 (adc_dovf_2),
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.adc_dovf_3 (adc_dovf_3),
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.adc_dsync (adc_dsync),
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.adc_dsync_0 (adc_dsync_0),
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.adc_dsync_1 (adc_dsync_1),
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.adc_dsync_2 (adc_dsync_2),
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.adc_dsync_3 (adc_dsync_3),
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.adc_dwr (adc_dwr),
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.adc_dwr_0 (adc_dwr_0),
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.adc_dwr_1 (adc_dwr_1),
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.adc_dwr_2 (adc_dwr_2),
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.adc_dwr_3 (adc_dwr_3),
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.gt_rx_data (gt_rx_data),
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.gt_rx_data_0 (gt_rx_data_0),
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.gt_rx_data_1 (gt_rx_data_1),
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.gt_rx_data_2 (gt_rx_data_2),
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.gt_rx_data_3 (gt_rx_data_3),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.mlo_clk (afe_mlo),
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.rx_data_n (rx_data_n),
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.rx_data_p (rx_data_p),
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.rx_ref_clk (rx_ref_clk),
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.rx_sync (rx_sync),
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.rx_sysref (rx_sysref),
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|
.spdif (spdif),
|
|
.spi_clk_i (spi_clk),
|
|
.spi_clk_o (spi_clk),
|
|
.spi_csn_i (spi_csn),
|
|
.spi_csn_o (spi_csn),
|
|
.spi_sdi_i (spi_miso),
|
|
.spi_sdo_i (spi_mosi),
|
|
.spi_sdo_o (spi_mosi));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
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