532 lines
14 KiB
Verilog
532 lines
14 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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ddr_addr,
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ddr_ba,
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ddr_cas_n,
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ddr_ck_n,
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ddr_ck_p,
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ddr_cke,
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ddr_cs_n,
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ddr_dm,
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ddr_dq,
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ddr_dqs_n,
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ddr_dqs_p,
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ddr_odt,
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ddr_ras_n,
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ddr_reset_n,
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ddr_we_n,
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eth1_mdc,
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eth1_mdio,
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eth1_rgmii_rxclk,
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eth1_rgmii_rxctl,
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eth1_rgmii_rxdata,
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eth1_rgmii_txclk,
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eth1_rgmii_txctl,
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eth1_rgmii_txdata,
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fixed_io_ddr_vrn,
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fixed_io_ddr_vrp,
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fixed_io_mio,
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fixed_io_ps_clk,
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fixed_io_ps_porb,
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fixed_io_ps_srstb,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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hdmi_pd,
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hdmi_intn,
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spdif,
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spdif_in,
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i2s_mclk,
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i2s_bclk,
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i2s_lrclk,
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i2s_sdata_out,
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i2s_sdata_in,
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iic_scl,
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iic_sda,
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gpio_bd,
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fan_pwm,
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fan_tach,
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clk_0_p,
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clk_0_n,
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clk_1_p,
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clk_1_n,
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gp_in_0,
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gp_inout_0,
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gp_inout_1,
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gp_inout,
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gp_out,
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gp_in,
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gt_ref_clk_0_p,
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gt_ref_clk_0_n,
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gt_ref_clk_1_p,
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gt_ref_clk_1_n,
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gt_tx_0_p,
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gt_tx_0_n,
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gt_rx_0_p,
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gt_rx_0_n,
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gt_tx_1_p,
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gt_tx_1_n,
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gt_rx_1_p,
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gt_rx_1_n,
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ad9517_csn,
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ad9517_clk,
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ad9517_mosi,
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ad9517_miso,
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ad9517_pdn,
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ad9517_ref_sel,
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ad9517_ld,
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ad9517_status,
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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enable,
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txnrx,
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clk_out,
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gpio_rf0,
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gpio_rf1,
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gpio_rf2,
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gpio_rf3,
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gpio_rfpwr_enable,
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gpio_clksel,
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gpio_resetb,
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gpio_sync,
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gpio_en_agc,
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gpio_ctl,
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gpio_status,
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spi_csn,
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spi_clk,
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spi_mosi,
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spi_miso);
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inout [14:0] ddr_addr;
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inout [ 2:0] ddr_ba;
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inout ddr_cas_n;
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inout ddr_ck_n;
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inout ddr_ck_p;
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inout ddr_cke;
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inout ddr_cs_n;
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inout [ 3:0] ddr_dm;
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inout [31:0] ddr_dq;
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inout [ 3:0] ddr_dqs_n;
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inout [ 3:0] ddr_dqs_p;
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inout ddr_odt;
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inout ddr_ras_n;
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inout ddr_reset_n;
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inout ddr_we_n;
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output eth1_mdc;
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inout eth1_mdio;
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input eth1_rgmii_rxclk;
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input eth1_rgmii_rxctl;
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input [ 3:0] eth1_rgmii_rxdata;
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output eth1_rgmii_txclk;
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output eth1_rgmii_txctl;
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output [ 3:0] eth1_rgmii_txdata;
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inout fixed_io_ddr_vrn;
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inout fixed_io_ddr_vrp;
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inout [53:0] fixed_io_mio;
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inout fixed_io_ps_clk;
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inout fixed_io_ps_porb;
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inout fixed_io_ps_srstb;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [15:0] hdmi_data;
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output hdmi_pd;
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input hdmi_intn;
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output spdif;
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input spdif_in;
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output i2s_mclk;
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output i2s_bclk;
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output i2s_lrclk;
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output i2s_sdata_out;
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input i2s_sdata_in;
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inout iic_scl;
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inout iic_sda;
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inout [11:0] gpio_bd;
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output fan_pwm;
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input fan_tach;
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input clk_0_p;
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input clk_0_n;
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input clk_1_p;
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input clk_1_n;
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input gp_in_0;
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inout gp_inout_0;
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inout gp_inout_1;
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inout [ 6:0] gp_inout;
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output [53:0] gp_out;
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input [53:0] gp_in;
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input gt_ref_clk_0_p;
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input gt_ref_clk_0_n;
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input gt_ref_clk_1_p;
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input gt_ref_clk_1_n;
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output gt_tx_0_p;
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output gt_tx_0_n;
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input gt_rx_0_p;
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input gt_rx_0_n;
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output gt_tx_1_p;
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output gt_tx_1_n;
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input gt_rx_1_p;
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input gt_rx_1_n;
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output ad9517_csn;
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output ad9517_clk;
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output ad9517_mosi;
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input ad9517_miso;
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inout ad9517_pdn;
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inout ad9517_ref_sel;
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inout ad9517_ld;
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inout ad9517_status;
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_n;
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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output enable;
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output txnrx;
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input clk_out;
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inout gpio_rf0;
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inout gpio_rf1;
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inout gpio_rf2;
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inout gpio_rf3;
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inout gpio_rfpwr_enable;
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inout gpio_clksel;
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inout gpio_resetb;
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inout gpio_sync;
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inout gpio_en_agc;
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inout [ 3:0] gpio_ctl;
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inout [ 7:0] gpio_status;
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output spi_csn;
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output spi_clk;
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output spi_mosi;
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input spi_miso;
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// internal signals
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wire [ 1:0] spi_csn_s;
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wire spi_clk_s;
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wire spi_mosi_s;
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wire spi_miso_s;
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wire clk_0;
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wire clk_1;
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wire gt_ref_clk_0;
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wire gt_ref_clk_1;
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wire [63:0] gp_ioenb_s;
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wire [63:0] gp_out_s;
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wire [63:0] gp_in_s;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire tdd_sync_i;
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wire tdd_sync_o;
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wire tdd_sync_t;
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// assignments
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assign fan_pwm = 1'b1;
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assign hdmi_pd = 1'b0;
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assign spi_csn = spi_csn_s[0];
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assign spi_clk = spi_clk_s;
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assign spi_mosi = spi_mosi_s;
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assign ad9517_csn = spi_csn_s[1];
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assign ad9517_clk = spi_clk_s;
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assign ad9517_mosi = spi_mosi_s;
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assign spi_miso_s = (~spi_csn_s[0] & spi_miso) | (~spi_csn_s[1] & ad9517_miso);
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// instantiations
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IBUFDS i_ibufds_clk_0 (
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.I (clk_0_p),
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.IB (clk_0_n),
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.O (clk_0));
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IBUFDS i_ibufds_clk_1 (
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.I (clk_1_p),
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.IB (clk_1_n),
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.O (clk_1));
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IBUFDS_GTE2 i_ibufds_gt_ref_clk_0 (
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.CEB (1'd0),
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.I (gt_ref_clk_0_p),
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.IB (gt_ref_clk_0_n),
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.O (gt_ref_clk_0),
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.ODIV2 ());
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IBUFDS_GTE2 i_ibufds_gt_ref_clk_1 (
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.CEB (1'd0),
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.I (gt_ref_clk_1_p),
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.IB (gt_ref_clk_1_n),
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.O (gt_ref_clk_1),
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.ODIV2 ());
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assign gp_out[53:0] = gp_out_s[53:0];
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assign gp_in_s[53:0] = gp_in[53:0];
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assign gp_in_s[63:63] = gp_in_0;
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assign gp_in_s[62:62] = gp_out_s[62];
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assign gp_in_s[54:54] = gp_out_s[62] & gpio_tdd_sync_i;
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ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_61_55 (
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.dio_t (gp_ioenb_s[61:55]),
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.dio_i (gp_out_s[61:55]),
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.dio_o (gp_in_s[61:55]),
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.dio_p (gp_inout));
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ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_54_0 (
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.dio_t (1'b0),
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.dio_i (gp_out_s[54]),
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.dio_o (),
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.dio_p (gp_inout_0));
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ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_54_1 (
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.dio_t (gpio_tdd_sync_t),
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.dio_i (gpio_tdd_sync_o),
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.dio_o (gpio_tdd_sync_i),
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.dio_p (gp_inout_1));
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assign gpio_tdd_sync_t = gp_out_s[62] | tdd_sync_t;
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assign gpio_tdd_sync_o = gp_out_s[62] | tdd_sync_o;
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assign tdd_sync_i = ~gp_out_s[62] & gpio_tdd_sync_i;
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ad_iobuf #(.DATA_WIDTH(25)) i_iobuf (
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.dio_t ({gpio_t[60:51], gpio_t[46:32]}),
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.dio_i ({gpio_o[60:51], gpio_o[46:32]}),
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.dio_o ({gpio_i[60:51], gpio_i[46:32]}),
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.dio_p ({ ad9517_pdn, // 60:60
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ad9517_ref_sel, // 59:59
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ad9517_ld, // 58:58
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ad9517_status, // 57:57
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gpio_rf0, // 56:56
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gpio_rf1, // 55:55
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gpio_rf2, // 54:54
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gpio_rf3, // 53:53
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gpio_rfpwr_enable, // 52:52
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gpio_clksel, // 51:51
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gpio_resetb, // 46:46
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gpio_sync, // 45:45
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gpio_en_agc, // 44:44
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gpio_ctl, // 43:40
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gpio_status})); // 39:32
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ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
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.dio_t (gpio_t[11:0]),
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.dio_i (gpio_o[11:0]),
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.dio_o (gpio_i[11:0]),
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.dio_p (gpio_bd));
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system_wrapper i_system_wrapper (
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.clk_0 (clk_0),
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.clk_1 (clk_1),
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.enable (enable),
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.eth1_125mclk (),
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.eth1_25mclk (),
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.eth1_2m5clk (),
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.eth1_clock_speed (),
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.eth1_duplex_status (),
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.eth1_intn (1'b1),
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.eth1_link_status (),
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.eth1_mdio_mdc (eth1_mdc),
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.eth1_mdio_mdio_io (eth1_mdio),
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.eth1_refclk (),
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.eth1_rgmii_rd (eth1_rgmii_rxdata),
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.eth1_rgmii_rx_ctl (eth1_rgmii_rxctl),
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.eth1_rgmii_rxc (eth1_rgmii_rxclk),
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.eth1_rgmii_td (eth1_rgmii_txdata),
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.eth1_rgmii_tx_ctl (eth1_rgmii_txctl),
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.eth1_rgmii_txc (eth1_rgmii_txclk),
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.eth1_speed_mode (),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gp_in_0 (gp_in_s[31:0]),
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.gp_in_1 (gp_in_s[63:32]),
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.gp_ioenb_0 (gp_ioenb_s[31:0]),
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.gp_ioenb_1 (gp_ioenb_s[63:32]),
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.gp_out_0 (gp_out_s[31:0]),
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.gp_out_1 (gp_out_s[63:32]),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.gt_ref_clk_0 (gt_ref_clk_0),
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.gt_ref_clk_1 (gt_ref_clk_1),
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.gt_rx_0_n (gt_rx_0_n),
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.gt_rx_0_p (gt_rx_0_p),
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.gt_rx_1_n (gt_rx_1_n),
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.gt_rx_1_p (gt_rx_1_p),
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.gt_tx_0_n (gt_tx_0_n),
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.gt_tx_0_p (gt_tx_0_p),
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.gt_tx_1_n (gt_tx_1_n),
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.gt_tx_1_p (gt_tx_1_p),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.i2s_bclk (i2s_bclk),
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.i2s_lrclk (i2s_lrclk),
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.i2s_mclk (i2s_mclk),
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.i2s_sdata_in (i2s_sdata_in),
|
|
.i2s_sdata_out (i2s_sdata_out),
|
|
.iic_main_scl_io (iic_scl),
|
|
.iic_main_sda_io (iic_sda),
|
|
.otg_vbusoc (1'b0),
|
|
.ps_intr_00 (1'b0),
|
|
.ps_intr_01 (1'b0),
|
|
.ps_intr_02 (1'b0),
|
|
.ps_intr_03 (1'b0),
|
|
.ps_intr_04 (1'b0),
|
|
.ps_intr_05 (1'b0),
|
|
.ps_intr_06 (1'b0),
|
|
.ps_intr_07 (1'b0),
|
|
.ps_intr_08 (1'b0),
|
|
.ps_intr_09 (1'b0),
|
|
.ps_intr_10 (1'b0),
|
|
.ps_intr_11 (1'b0),
|
|
.rx_clk_in_n (rx_clk_in_n),
|
|
.rx_clk_in_p (rx_clk_in_p),
|
|
.rx_data_in_n (rx_data_in_n),
|
|
.rx_data_in_p (rx_data_in_p),
|
|
.rx_frame_in_n (rx_frame_in_n),
|
|
.rx_frame_in_p (rx_frame_in_p),
|
|
.spdif (spdif),
|
|
.spi0_clk_i (1'b0),
|
|
.spi0_clk_o (spi_clk_s),
|
|
.spi0_csn_0_o (spi_csn_s[0]),
|
|
.spi0_csn_1_o (spi_csn_s[1]),
|
|
.spi0_csn_2_o (),
|
|
.spi0_csn_i (1'b1),
|
|
.spi0_sdi_i (spi_miso_s),
|
|
.spi0_sdo_i (1'b0),
|
|
.spi0_sdo_o (spi_mosi_s),
|
|
.spi1_clk_i (1'b0),
|
|
.spi1_clk_o (),
|
|
.spi1_csn_0_o (),
|
|
.spi1_csn_1_o (),
|
|
.spi1_csn_2_o (),
|
|
.spi1_csn_i (1'b1),
|
|
.spi1_sdi_i (1'b0),
|
|
.spi1_sdo_i (1'b0),
|
|
.spi1_sdo_o (),
|
|
.tdd_sync_i (tdd_sync_i),
|
|
.tdd_sync_o (tdd_sync_o),
|
|
.tdd_sync_t (tdd_sync_t),
|
|
.tx_clk_out_n (tx_clk_out_n),
|
|
.tx_clk_out_p (tx_clk_out_p),
|
|
.tx_data_out_n (tx_data_out_n),
|
|
.tx_data_out_p (tx_data_out_p),
|
|
.tx_frame_out_n (tx_frame_out_n),
|
|
.tx_frame_out_p (tx_frame_out_p),
|
|
.txnrx (txnrx),
|
|
.up_enable (gpio_o[47]),
|
|
.up_txnrx (gpio_o[48]));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|