Istvan Csomortani db0cd63ed3 axi_ad9361: Fix Warning[Synth 8-2611] ... In Verilog-2001 standard, redeclaration of an output port as a wire is not allowed.		2017-04-19 13:52:13 +03:00
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altera	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
xilinx	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
Makefile	Makefile: Update Makefiles for libraries	2017-03-30 18:33:22 +03:00
axi_ad9361.v	axi_ad9361- add receive init delay	2017-03-13 16:28:38 -04:00
axi_ad9361_constr.sdc	library/axi_ad9361: tdd false paths	2016-05-04 13:42:12 -04:00
axi_ad9361_constr.xdc	axi_ad9361: Define CDC constraint for tdd_sync	2017-02-24 11:24:07 +02:00
axi_ad9361_delay.tcl	move/rename - delay script belongs to ad9361	2017-03-10 12:44:32 -05:00
axi_ad9361_hw.tcl	alt_serdes- a10 ddio fixes	2016-11-01 12:41:25 -04:00
axi_ad9361_ip.tcl	library: Delete all adi_ip_constraint process call	2017-04-06 12:36:47 +03:00
axi_ad9361_rx.v	axi_ad9361- add receive init delay	2017-03-13 16:28:38 -04:00
axi_ad9361_rx_channel.v	…
axi_ad9361_rx_pnmon.v	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
axi_ad9361_tdd.v	axi_ad9361: Fix Warning[Synth 8-2611]	2017-04-19 13:52:13 +03:00
axi_ad9361_tdd_if.v	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
axi_ad9361_tx.v	axi_ad9361- add receive init delay	2017-03-13 16:28:38 -04:00
axi_ad9361_tx_channel.v	…