154 lines
5.0 KiB
Verilog
154 lines
5.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// iq correction = a*(i+x) + b*(q+y); offsets are added in dcfilter.
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`timescale 1ns/100ps
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module ad_iqcor #(
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// select i/q if disabled
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parameter Q_OR_I_N = 0,
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parameter DISABLE = 0) (
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// data interface
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input clk,
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input valid,
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input [15:0] data_in,
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input [15:0] data_iq,
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output valid_out,
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output [15:0] data_out,
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// control interface
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input iqcor_enable,
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input [15:0] iqcor_coeff_1,
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input [15:0] iqcor_coeff_2);
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// internal registers
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reg p1_valid = 'd0;
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reg [15:0] p1_data_i = 'd0;
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reg [15:0] p1_data_q = 'd0;
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reg [33:0] p1_data_p = 'd0;
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reg valid_int = 'd0;
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reg [15:0] data_int = 'd0;
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reg [15:0] iqcor_coeff_1_r = 'd0;
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reg [15:0] iqcor_coeff_2_r = 'd0;
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// internal signals
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wire [15:0] data_i_s;
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wire [15:0] data_q_s;
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wire [33:0] p1_data_p_i_s;
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wire p1_valid_s;
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wire [15:0] p1_data_i_s;
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wire [33:0] p1_data_p_q_s;
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wire [15:0] p1_data_q_s;
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// data-path disable
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generate
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if (DISABLE == 1) begin
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assign valid_out = valid;
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assign data_out = data_in;
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end else begin
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assign valid_out = valid_int;
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assign data_out = data_int;
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end
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endgenerate
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// swap i & q
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assign data_i_s = (Q_OR_I_N == 1) ? data_iq : data_in;
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assign data_q_s = (Q_OR_I_N == 1) ? data_in : data_iq;
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// coefficients are flopped to remove warnings from vivado
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always @(posedge clk) begin
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iqcor_coeff_1_r <= iqcor_coeff_1;
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iqcor_coeff_2_r <= iqcor_coeff_2;
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end
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// scaling functions - i
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ad_mul #(.DELAY_DATA_WIDTH(17)) i_mul_i (
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.clk (clk),
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.data_a ({data_i_s[15], data_i_s}),
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.data_b ({iqcor_coeff_1_r[15], iqcor_coeff_1_r}),
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.data_p (p1_data_p_i_s),
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.ddata_in ({valid, data_i_s}),
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.ddata_out ({p1_valid_s, p1_data_i_s}));
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// scaling functions - q
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ad_mul #(.DELAY_DATA_WIDTH(16)) i_mul_q (
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.clk (clk),
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.data_a ({data_q_s[15], data_q_s}),
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.data_b ({iqcor_coeff_2_r[15], iqcor_coeff_2_r}),
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.data_p (p1_data_p_q_s),
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.ddata_in (data_q_s),
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.ddata_out (p1_data_q_s));
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// sum
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always @(posedge clk) begin
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p1_valid <= p1_valid_s;
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p1_data_i <= p1_data_i_s;
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p1_data_q <= p1_data_q_s;
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p1_data_p <= p1_data_p_i_s + p1_data_p_q_s;
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end
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// output registers
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always @(posedge clk) begin
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valid_int <= p1_valid;
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if (iqcor_enable == 1'b1) begin
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data_int <= p1_data_p[29:14];
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end else if (Q_OR_I_N == 1) begin
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data_int <= p1_data_q;
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end else begin
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data_int <= p1_data_i;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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