185 lines
6.9 KiB
Verilog
185 lines
6.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// Color Space Conversion, multiplier. This is a simple partial product adder
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// that generates the product of the two inputs.
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`timescale 1ps/1ps
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module ad_csc_1_mul (
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// data_a is signed
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clk,
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data_a,
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data_b,
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data_p,
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// delay match
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ddata_in,
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ddata_out);
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// parameters
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parameter DELAY_DATA_WIDTH = 16;
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localparam DW = DELAY_DATA_WIDTH - 1;
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// data_a is signed
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input clk;
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input [16:0] data_a;
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input [ 7:0] data_b;
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output [24:0] data_p;
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// delay match
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input [DW:0] ddata_in;
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output [DW:0] ddata_out;
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// internal registers
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reg p1_sign = 'd0;
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reg [DW:0] p1_ddata = 'd0;
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reg [23:0] p1_data_p_0 = 'd0;
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reg [23:0] p1_data_p_1 = 'd0;
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reg [23:0] p1_data_p_2 = 'd0;
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reg [23:0] p1_data_p_3 = 'd0;
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reg [23:0] p1_data_p_4 = 'd0;
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reg p2_sign = 'd0;
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reg [DW:0] p2_ddata = 'd0;
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reg [23:0] p2_data_p_0 = 'd0;
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reg [23:0] p2_data_p_1 = 'd0;
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reg p3_sign = 'd0;
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reg [DW:0] p3_ddata = 'd0;
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reg [23:0] p3_data_p_0 = 'd0;
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reg [DW:0] ddata_out = 'd0;
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reg [24:0] data_p = 'd0;
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// internal wires
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wire [16:0] p1_data_a_1p_17_s;
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wire [16:0] p1_data_a_1n_17_s;
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wire [23:0] p1_data_a_1p_s;
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wire [23:0] p1_data_a_1n_s;
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wire [23:0] p1_data_a_2p_s;
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wire [23:0] p1_data_a_2n_s;
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// pipe line stage 1, get the two's complement versions
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assign p1_data_a_1p_17_s = {1'b0, data_a[15:0]};
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assign p1_data_a_1n_17_s = ~p1_data_a_1p_17_s + 1'b1;
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assign p1_data_a_1p_s = {{7{p1_data_a_1p_17_s[16]}}, p1_data_a_1p_17_s};
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assign p1_data_a_1n_s = {{7{p1_data_a_1n_17_s[16]}}, p1_data_a_1n_17_s};
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assign p1_data_a_2p_s = {{6{p1_data_a_1p_17_s[16]}}, p1_data_a_1p_17_s, 1'b0};
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assign p1_data_a_2n_s = {{6{p1_data_a_1n_17_s[16]}}, p1_data_a_1n_17_s, 1'b0};
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// pipe line stage 1, get the partial products
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always @(posedge clk) begin
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p1_sign <= data_a[16];
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p1_ddata <= ddata_in;
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case (data_b[1:0])
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2'b11: p1_data_p_0 <= p1_data_a_1n_s;
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2'b10: p1_data_p_0 <= p1_data_a_2n_s;
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2'b01: p1_data_p_0 <= p1_data_a_1p_s;
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default: p1_data_p_0 <= 24'd0;
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endcase
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case (data_b[3:1])
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3'b011: p1_data_p_1 <= {p1_data_a_2p_s[21:0], 2'd0};
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3'b100: p1_data_p_1 <= {p1_data_a_2n_s[21:0], 2'd0};
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3'b001: p1_data_p_1 <= {p1_data_a_1p_s[21:0], 2'd0};
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3'b010: p1_data_p_1 <= {p1_data_a_1p_s[21:0], 2'd0};
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3'b101: p1_data_p_1 <= {p1_data_a_1n_s[21:0], 2'd0};
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3'b110: p1_data_p_1 <= {p1_data_a_1n_s[21:0], 2'd0};
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default: p1_data_p_1 <= 24'd0;
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endcase
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case (data_b[5:3])
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3'b011: p1_data_p_2 <= {p1_data_a_2p_s[19:0], 4'd0};
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3'b100: p1_data_p_2 <= {p1_data_a_2n_s[19:0], 4'd0};
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3'b001: p1_data_p_2 <= {p1_data_a_1p_s[19:0], 4'd0};
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3'b010: p1_data_p_2 <= {p1_data_a_1p_s[19:0], 4'd0};
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3'b101: p1_data_p_2 <= {p1_data_a_1n_s[19:0], 4'd0};
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3'b110: p1_data_p_2 <= {p1_data_a_1n_s[19:0], 4'd0};
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default: p1_data_p_2 <= 24'd0;
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endcase
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case (data_b[7:5])
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3'b011: p1_data_p_3 <= {p1_data_a_2p_s[17:0], 6'd0};
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3'b100: p1_data_p_3 <= {p1_data_a_2n_s[17:0], 6'd0};
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3'b001: p1_data_p_3 <= {p1_data_a_1p_s[17:0], 6'd0};
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3'b010: p1_data_p_3 <= {p1_data_a_1p_s[17:0], 6'd0};
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3'b101: p1_data_p_3 <= {p1_data_a_1n_s[17:0], 6'd0};
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3'b110: p1_data_p_3 <= {p1_data_a_1n_s[17:0], 6'd0};
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default: p1_data_p_3 <= 24'd0;
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endcase
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case (data_b[7])
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1'b1: p1_data_p_4 <= {p1_data_a_1p_s[15:0], 8'd0};
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default: p1_data_p_4 <= 24'd0;
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endcase
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end
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// pipe line stage 2, get the sum (intermediate 5 -> 2)
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always @(posedge clk) begin
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p2_sign <= p1_sign;
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p2_ddata <= p1_ddata;
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p2_data_p_0 <= p1_data_p_0 + p1_data_p_1 + p1_data_p_4;
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p2_data_p_1 <= p1_data_p_2 + p1_data_p_3;
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end
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// pipe line stage 2, get the sum (final 2 -> 1)
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always @(posedge clk) begin
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p3_sign <= p2_sign;
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p3_ddata <= p2_ddata;
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p3_data_p_0 <= p2_data_p_0 + p2_data_p_1;
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end
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// output registers (truncation occurs after addition, see ad_csc_1_add.v)
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always @(posedge clk) begin
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ddata_out <= p3_ddata;
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data_p <= {p3_sign, p3_data_p_0};
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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