221 lines
7.9 KiB
Tcl
221 lines
7.9 KiB
Tcl
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 adc1_spi
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 adc2_spi
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create_bd_port -dir I adc1_data_ready
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create_bd_port -dir I adc2_data_ready
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# create a SPI Engine architecture for both ADCs
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create_bd_cell -type hier spi_adc1
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current_bd_instance /spi_adc1
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir I drdy
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
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# DATA_WIDTH is set to 8, so the granularity of the transaction will be 8 bit
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# So we can to support 16bit 24bit and 32bit transfers
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ad_ip_instance spi_engine_execution execution
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ad_ip_parameter execution CONFIG.DATA_WIDTH 8
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ad_ip_parameter execution CONFIG.NUM_OF_CS 1
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ad_ip_instance axi_spi_engine axi_1
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ad_ip_parameter axi_1 CONFIG.DATA_WIDTH 8
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ad_ip_parameter axi_1 CONFIG.NUM_OFFLOAD 1
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ad_ip_instance spi_engine_offload offload
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ad_ip_parameter offload CONFIG.DATA_WIDTH 8
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ad_ip_parameter offload CONFIG.ASYNC_TRIG 1
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ad_ip_instance spi_engine_interconnect interconnect
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ad_ip_parameter interconnect CONFIG.DATA_WIDTH 8
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# to convert the 8bit AXI stream to 24bit AXI stream
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ad_ip_instance axis_dwidth_converter m_axis_samples_24
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ad_ip_parameter m_axis_samples_24 CONFIG.M_TDATA_NUM_BYTES 3
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# upscale the data to 32bit, samples should be multiple of 16bit
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ad_ip_instance util_axis_upscale axis_upscaler
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ad_ip_parameter axis_upscaler CONFIG.NUM_OF_CHANNELS 1
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ad_ip_parameter axis_upscaler CONFIG.DATA_WIDTH 24
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ad_ip_parameter axis_upscaler CONFIG.UDATA_WIDTH 32
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ad_connect axis_upscaler/dfmt_enable GND
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ad_connect axis_upscaler/dfmt_type GND
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ad_connect axis_upscaler/dfmt_se GND
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ad_connect axi_1/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi_1/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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ad_connect offload/offload_sdi m_axis_samples_24/S_AXIS
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ad_connect m_axis_samples_24/M_AXIS axis_upscaler/s_axis
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ad_connect axis_upscaler/m_axis M_AXIS_SAMPLE
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ad_connect execution/spi m_spi
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ad_connect clk offload/spi_clk
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ad_connect clk offload/ctrl_clk
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ad_connect clk execution/clk
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ad_connect clk axi_1/s_axi_aclk
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ad_connect clk axi_1/spi_clk
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ad_connect clk interconnect/clk
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ad_connect clk m_axis_samples_24/aclk
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ad_connect clk axis_upscaler/clk
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ad_connect axi_1/spi_resetn offload/spi_resetn
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ad_connect axi_1/spi_resetn execution/resetn
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ad_connect axi_1/spi_resetn interconnect/resetn
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ad_connect axi_1/spi_resetn m_axis_samples_24/aresetn
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ad_connect axi_1/spi_resetn axis_upscaler/resetn
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ad_connect drdy offload/trigger
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ad_connect resetn axi_1/s_axi_aresetn
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ad_connect irq axi_1/irq
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current_bd_instance /
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create_bd_cell -type hier spi_adc2
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current_bd_instance /spi_adc2
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir I drdy
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
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ad_ip_instance spi_engine_execution execution
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ad_ip_parameter execution CONFIG.DATA_WIDTH 8
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ad_ip_parameter execution CONFIG.NUM_OF_CS 1
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ad_ip_instance axi_spi_engine axi_2
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ad_ip_parameter axi_2 CONFIG.DATA_WIDTH 8
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ad_ip_parameter axi_2 CONFIG.NUM_OFFLOAD 1
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ad_ip_instance spi_engine_offload offload
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ad_ip_parameter offload CONFIG.DATA_WIDTH 8
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ad_ip_parameter offload CONFIG.ASYNC_TRIG 1
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ad_ip_instance spi_engine_interconnect interconnect
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ad_ip_parameter interconnect CONFIG.DATA_WIDTH 8
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# to convert the 8bit AXI stream to 24bit AXI stream
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ad_ip_instance axis_dwidth_converter m_axis_samples_24
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ad_ip_parameter m_axis_samples_24 CONFIG.M_TDATA_NUM_BYTES 3
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# upscale the data to 32bit, samples should be multiple of 16bit
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ad_ip_instance util_axis_upscale axis_upscaler
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ad_ip_parameter axis_upscaler CONFIG.NUM_OF_CHANNELS 1
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ad_ip_parameter axis_upscaler CONFIG.DATA_WIDTH 24
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ad_ip_parameter axis_upscaler CONFIG.UDATA_WIDTH 32
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ad_connect axis_upscaler/dfmt_enable GND
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ad_connect axis_upscaler/dfmt_type GND
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ad_connect axis_upscaler/dfmt_se GND
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ad_connect axi_2/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi_2/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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ad_connect offload/offload_sdi m_axis_samples_24/S_AXIS
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ad_connect m_axis_samples_24/M_AXIS axis_upscaler/s_axis
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ad_connect axis_upscaler/m_axis M_AXIS_SAMPLE
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ad_connect execution/spi m_spi
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ad_connect clk offload/spi_clk
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ad_connect clk offload/ctrl_clk
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ad_connect clk execution/clk
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ad_connect clk axi_2/s_axi_aclk
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ad_connect clk axi_2/spi_clk
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ad_connect clk interconnect/clk
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ad_connect clk m_axis_samples_24/aclk
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ad_connect clk axis_upscaler/clk
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ad_connect axi_2/spi_resetn offload/spi_resetn
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ad_connect axi_2/spi_resetn execution/resetn
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ad_connect axi_2/spi_resetn interconnect/resetn
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ad_connect axi_2/spi_resetn m_axis_samples_24/aresetn
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ad_connect axi_2/spi_resetn axis_upscaler/resetn
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ad_connect drdy offload/trigger
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ad_connect resetn axi_2/s_axi_aresetn
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ad_connect irq axi_2/irq
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current_bd_instance /
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ad_connect adc1_data_ready spi_adc1/drdy
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ad_connect adc2_data_ready spi_adc2/drdy
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# dma for the ADC1
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ad_ip_instance axi_dmac axi_ad77681_dma_1
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ad_ip_parameter axi_ad77681_dma_1 CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad77681_dma_1 CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad77681_dma_1 CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad77681_dma_1 CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad77681_dma_1 CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad77681_dma_1 CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad77681_dma_1 CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad77681_dma_1 CONFIG.DMA_DATA_WIDTH_SRC 32
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ad_ip_parameter axi_ad77681_dma_1 CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_connect sys_cpu_clk spi_adc1/clk
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ad_connect sys_cpu_resetn spi_adc1/resetn
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ad_connect sys_cpu_resetn axi_ad77681_dma_1/m_dest_axi_aresetn
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ad_connect spi_adc1/m_spi adc1_spi
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ad_connect axi_ad77681_dma_1/s_axis spi_adc1/M_AXIS_SAMPLE
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# dma for the ADC2
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ad_ip_instance axi_dmac axi_ad77681_dma_2
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ad_ip_parameter axi_ad77681_dma_2 CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad77681_dma_2 CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad77681_dma_2 CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad77681_dma_2 CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad77681_dma_2 CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad77681_dma_2 CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad77681_dma_2 CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad77681_dma_2 CONFIG.DMA_DATA_WIDTH_SRC 32
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ad_ip_parameter axi_ad77681_dma_2 CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_connect sys_cpu_clk spi_adc2/clk
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ad_connect sys_cpu_resetn spi_adc2/resetn
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ad_connect sys_cpu_resetn axi_ad77681_dma_2/m_dest_axi_aresetn
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ad_connect spi_adc2/m_spi adc2_spi
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ad_connect axi_ad77681_dma_2/s_axis spi_adc2/M_AXIS_SAMPLE
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# AXI address definitions
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ad_cpu_interconnect 0x44a00000 spi_adc1/axi_1
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ad_cpu_interconnect 0x44b00000 spi_adc2/axi_2
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ad_cpu_interconnect 0x44a30000 axi_ad77681_dma_1
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ad_cpu_interconnect 0x44b30000 axi_ad77681_dma_2
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ad_connect sys_cpu_clk axi_ad77681_dma_1/s_axis_aclk
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ad_connect sys_cpu_clk axi_ad77681_dma_2/s_axis_aclk
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# interrupts
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ad_cpu_interrupt "ps-13" "mb-13" axi_ad77681_dma_1/irq
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ad_cpu_interrupt "ps-12" "mb-12" axi_ad77681_dma_2/irq
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ad_cpu_interrupt "ps-11" "mb-11" spi_adc1/irq
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ad_cpu_interrupt "ps-10" "mb-10" spi_adc2/irq
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# memory interconnects
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad77681_dma_1/m_dest_axi
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ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect sys_cpu_clk axi_ad77681_dma_2/m_dest_axi
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