15 lines
412 B
Tcl
15 lines
412 B
Tcl
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## FIFO depth is 4Mb - 250k samples
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set adc_fifo_address_width 16
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## FIFO depth is 4Mb - 250k samples
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set dac_fifo_address_width 15
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## NOTE: With this configuration the #36Kb BRAM utilization is at ~80%
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source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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source ../common/daq2_bd.tcl
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