448 lines
12 KiB
VHDL
448 lines
12 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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library work;
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use work.i2s_controller;
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library work;
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use work.axi_streaming_dma_rx_fifo;
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use work.axi_streaming_dma_tx_fifo;
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use work.pl330_dma_fifo;
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use work.axi_ctrlif;
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entity axi_i2s_adi is
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generic
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(
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-- ADD USER GENERICS BELOW THIS LINE ---------------
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SLOT_WIDTH : integer := 24;
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LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
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BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
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-- ADD USER GENERICS ABOVE THIS LINE ---------------
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- Bus protocol parameters, do not add to or delete
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S_AXI_DATA_WIDTH : integer := 32;
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S_AXI_ADDRESS_WIDTH : integer := 32;
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DEVICE_FAMILY : string := "virtex6";
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-- DO NOT EDIT ABOVE THIS LINE ---------------------
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DMA_TYPE : integer := 0;
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NUM_OF_CHANNEL : integer := 1;
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HAS_TX : integer := 1;
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HAS_RX : integer := 1
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);
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port
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(
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-- Serial Data interface
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DATA_CLK_I : in std_logic;
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BCLK_O : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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LRCLK_O : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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SDATA_O : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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SDATA_I : in std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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-- AXI Streaming DMA TX interface
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S_AXIS_ACLK : in std_logic;
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S_AXIS_ARESETN : in std_logic;
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S_AXIS_TREADY : out std_logic;
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S_AXIS_TDATA : in std_logic_vector(31 downto 0);
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S_AXIS_TLAST : in std_logic;
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S_AXIS_TVALID : in std_logic;
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-- AXI Streaming DMA RX interface
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M_AXIS_ACLK : in std_logic;
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M_AXIS_TREADY : in std_logic;
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M_AXIS_TDATA : out std_logic_vector(31 downto 0);
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M_AXIS_TLAST : out std_logic;
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M_AXIS_TVALID : out std_logic;
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M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
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--PL330 DMA TX interface
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DMA_REQ_TX_ACLK : in std_logic;
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DMA_REQ_TX_RSTN : in std_logic;
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DMA_REQ_TX_DAVALID : in std_logic;
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DMA_REQ_TX_DATYPE : in std_logic_vector(1 downto 0);
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DMA_REQ_TX_DAREADY : out std_logic;
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DMA_REQ_TX_DRVALID : out std_logic;
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DMA_REQ_TX_DRTYPE : out std_logic_vector(1 downto 0);
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DMA_REQ_TX_DRLAST : out std_logic;
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DMA_REQ_TX_DRREADY : in std_logic;
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-- PL330 DMA RX interface
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DMA_REQ_RX_ACLK : in std_logic;
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DMA_REQ_RX_RSTN : in std_logic;
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DMA_REQ_RX_DAVALID : in std_logic;
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DMA_REQ_RX_DATYPE : in std_logic_vector(1 downto 0);
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DMA_REQ_RX_DAREADY : out std_logic;
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DMA_REQ_RX_DRVALID : out std_logic;
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DMA_REQ_RX_DRTYPE : out std_logic_vector(1 downto 0);
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DMA_REQ_RX_DRLAST : out std_logic;
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DMA_REQ_RX_DRREADY : in std_logic;
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-- AXI bus interface
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S_AXI_ACLK : in std_logic;
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S_AXI_ARESETN : in std_logic;
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S_AXI_AWADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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S_AXI_AWVALID : in std_logic;
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S_AXI_WDATA : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_WSTRB : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
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S_AXI_WVALID : in std_logic;
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S_AXI_BREADY : in std_logic;
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S_AXI_ARADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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S_AXI_ARVALID : in std_logic;
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S_AXI_RREADY : in std_logic;
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S_AXI_ARREADY : out std_logic;
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S_AXI_RDATA : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_RRESP : out std_logic_vector(1 downto 0);
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S_AXI_RVALID : out std_logic;
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S_AXI_WREADY : out std_logic;
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S_AXI_BRESP : out std_logic_vector(1 downto 0);
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S_AXI_BVALID : out std_logic;
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S_AXI_AWREADY : out std_logic;
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S_AXI_AWPROT : in std_logic_vector(2 downto 0);
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S_AXI_ARPROT : in std_logic_vector(2 downto 0)
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);
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end entity axi_i2s_adi;
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architecture Behavioral of axi_i2s_adi is
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------------------------------------------
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-- Signals for user logic slave model s/w accessible register example
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------------------------------------------
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signal i2s_reset : std_logic;
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signal tx_fifo_reset : std_logic;
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signal tx_enable : Boolean;
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signal tx_data : std_logic_vector(SLOT_WIDTH - 1 downto 0);
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signal tx_ack : std_logic;
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signal tx_stb : std_logic;
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signal rx_enable : Boolean;
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signal rx_fifo_reset : std_logic;
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signal rx_data : std_logic_vector(SLOT_WIDTH - 1 downto 0);
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signal rx_ack : std_logic;
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signal rx_stb : std_logic;
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signal const_1 : std_logic;
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signal bclk_div_rate : natural range 0 to 255;
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signal lrclk_div_rate : natural range 0 to 255;
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signal period_len : integer range 0 to 65535;
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signal I2S_RESET_REG : std_logic_vector(31 downto 0);
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signal I2S_CONTROL_REG : std_logic_vector(31 downto 0);
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signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0);
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signal PERIOD_LEN_REG : std_logic_vector(31 downto 0);
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constant FIFO_AWIDTH : integer := integer(ceil(log2(real(NUM_OF_CHANNEL * 8))));
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-- Audio samples FIFO
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constant RAM_ADDR_WIDTH : integer := 7;
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type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0);
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-- RX FIFO signals
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signal audio_fifo_rx : RAM_TYPE;
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signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
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signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
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signal tvalid : std_logic := '0';
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signal rx_tlast : std_logic;
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signal drain_tx_dma : std_logic;
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signal rx_sample : std_logic_vector(23 downto 0);
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signal wr_data : std_logic_vector(31 downto 0);
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signal rd_data : std_logic_vector(31 downto 0);
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signal wr_addr : integer range 0 to 11;
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signal rd_addr : integer range 0 to 11;
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signal wr_stb : std_logic;
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signal rd_ack : std_logic;
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signal tx_fifo_stb : std_logic;
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signal rx_fifo_ack : std_logic;
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signal cnt : integer range 0 to 2**16-1;
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begin
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const_1 <= '1';
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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cnt <= 0;
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else
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cnt <= (cnt + 1) mod 2**16;
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end if;
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end if;
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end process;
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streaming_dma_tx_gen: if DMA_TYPE = 0 and HAS_TX = 1 generate
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tx_fifo : entity axi_streaming_dma_tx_fifo
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generic map(
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RAM_ADDR_WIDTH => FIFO_AWIDTH,
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FIFO_DWIDTH => 24
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)
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port map(
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clk => S_AXI_ACLK,
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resetn => S_AXI_ARESETN,
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fifo_reset => tx_fifo_reset,
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enable => tx_enable,
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S_AXIS_ACLK => S_AXIS_ACLK,
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S_AXIS_TREADY => S_AXIS_TREADY,
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S_AXIS_TDATA => S_AXIS_TDATA(31 downto 8),
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S_AXIS_TLAST => S_AXIS_TLAST,
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S_AXIS_TVALID => S_AXIS_TVALID,
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out_stb => tx_stb,
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out_ack => tx_ack,
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out_data => tx_data
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);
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end generate;
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no_streaming_dma_tx_gen: if DMA_TYPE /= 0 or HAS_TX /= 1 generate
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S_AXIS_TREADY <= '0';
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end generate;
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streaming_dma_rx_gen: if DMA_TYPE = 0 and HAS_RX = 1 generate
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rx_fifo : entity axi_streaming_dma_rx_fifo
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generic map(
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RAM_ADDR_WIDTH => FIFO_AWIDTH,
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FIFO_DWIDTH => 24
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)
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port map(
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clk => S_AXI_ACLK,
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resetn => S_AXI_ARESETN,
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fifo_reset => tx_fifo_reset,
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enable => tx_enable,
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period_len => period_len,
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in_stb => rx_stb,
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in_ack => rx_ack,
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in_data => rx_data,
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M_AXIS_ACLK => M_AXIS_ACLK,
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M_AXIS_TREADY => M_AXIS_TREADY,
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M_AXIS_TDATA => M_AXIS_TDATA(31 downto 8),
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M_AXIS_TLAST => M_AXIS_TLAST,
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M_AXIS_TVALID => M_AXIS_TVALID,
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M_AXIS_TKEEP => M_AXIS_TKEEP
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);
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M_AXIS_TDATA(7 downto 0) <= (others => '0');
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end generate;
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no_streaming_dma_rx_gen: if DMA_TYPE /= 0 or HAS_RX /= 1 generate
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M_AXIS_TDATA <= (others => '0');
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M_AXIS_TLAST <= '0';
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M_AXIS_TVALID <= '0';
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M_AXIS_TKEEP <= (others => '0');
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end generate;
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pl330_dma_tx_gen: if DMA_TYPE = 1 and HAS_TX = 1 generate
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tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0';
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tx_fifo: entity pl330_dma_fifo
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generic map(
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RAM_ADDR_WIDTH => FIFO_AWIDTH,
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FIFO_DWIDTH => 24,
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FIFO_DIRECTION => 0
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)
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port map (
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clk => S_AXI_ACLK,
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resetn => S_AXI_ARESETN,
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fifo_reset => tx_fifo_reset,
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enable => tx_enable,
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in_data => wr_data(31 downto 8),
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in_stb => tx_fifo_stb,
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out_ack => tx_ack,
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out_stb => tx_stb,
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out_data => tx_data,
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dclk => DMA_REQ_TX_ACLK,
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dresetn => DMA_REQ_TX_RSTN,
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davalid => DMA_REQ_TX_DAVALID,
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daready => DMA_REQ_TX_DAREADY,
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datype => DMA_REQ_TX_DATYPE,
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drvalid => DMA_REQ_TX_DRVALID,
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drready => DMA_REQ_TX_DRREADY,
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drtype => DMA_REQ_TX_DRTYPE,
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drlast => DMA_REQ_TX_DRLAST
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);
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end generate;
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no_pl330_dma_tx_gen: if DMA_TYPE /= 1 or HAS_TX /= 1 generate
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DMA_REQ_TX_DAREADY <= '0';
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DMA_REQ_TX_DRVALID <= '0';
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DMA_REQ_TX_DRTYPE <= (others => '0');
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DMA_REQ_TX_DRLAST <= '0';
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end generate;
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pl330_dma_rx_gen: if DMA_TYPE = 1 and HAS_RX = 1 generate
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rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0';
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rx_fifo: entity pl330_dma_fifo
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generic map(
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RAM_ADDR_WIDTH => FIFO_AWIDTH,
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FIFO_DWIDTH => 24,
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FIFO_DIRECTION => 1
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)
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port map (
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clk => S_AXI_ACLK,
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resetn => S_AXI_ARESETN,
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fifo_reset => rx_fifo_reset,
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enable => rx_enable,
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in_ack => rx_ack,
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in_stb => rx_stb,
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in_data => rx_data,
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out_data => rx_sample,
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out_ack => rx_fifo_ack,
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dclk => DMA_REQ_RX_ACLK,
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dresetn => DMA_REQ_RX_RSTN,
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davalid => DMA_REQ_RX_DAVALID,
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daready => DMA_REQ_RX_DAREADY,
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datype => DMA_REQ_RX_DATYPE,
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drvalid => DMA_REQ_RX_DRVALID,
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drready => DMA_REQ_RX_DRREADY,
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drtype => DMA_REQ_RX_DRTYPE,
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drlast => DMA_REQ_RX_DRLAST
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);
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end generate;
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no_pl330_dma_rx_gen: if DMA_TYPE /= 1 or HAS_RX /= 1 generate
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DMA_REQ_RX_DAREADY <= '0';
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DMA_REQ_RX_DRVALID <= '0';
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DMA_REQ_RX_DRTYPE <= (others => '0');
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DMA_REQ_RX_DRLAST <= '0';
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end generate;
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ctrl : entity i2s_controller
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generic map (
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C_SLOT_WIDTH => SLOT_WIDTH,
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C_BCLK_POL => BCLK_POL,
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C_LRCLK_POL => LRCLK_POL,
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C_NUM_CH => NUM_OF_CHANNEL,
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C_HAS_TX => HAS_TX,
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C_HAS_RX => HAS_RX
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)
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port map (
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clk => S_AXI_ACLK,
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resetn => S_AXI_ARESETN,
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data_clk => DATA_CLK_I,
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BCLK_O => BCLK_O,
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LRCLK_O => LRCLK_O,
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SDATA_O => SDATA_O,
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SDATA_I => SDATA_I,
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tx_enable => tx_enable,
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tx_ack => tx_ack,
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tx_stb => tx_stb,
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tx_data => tx_data,
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rx_enable => rx_enable,
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rx_ack => rx_ack,
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rx_stb => rx_stb,
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rx_data => rx_data,
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bclk_div_rate => bclk_div_rate,
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lrclk_div_rate => lrclk_div_rate
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);
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i2s_reset <= I2S_RESET_REG(0);
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tx_fifo_reset <= I2S_RESET_REG(1);
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rx_fifo_reset <= I2S_RESET_REG(2);
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tx_enable <= I2S_CONTROL_REG(0) = '1';
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rx_enable <= I2S_CONTROL_REG(1) = '1';
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bclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(7 downto 0)));
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lrclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(23 downto 16)));
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period_len <= to_integer(unsigned(PERIOD_LEN_REG(15 downto 0)));
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ctrlif: entity axi_ctrlif
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generic map (
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C_S_AXI_ADDR_WIDTH => S_AXI_ADDRESS_WIDTH,
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C_S_AXI_DATA_WIDTH => S_AXI_DATA_WIDTH,
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C_NUM_REG => 12
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)
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port map(
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S_AXI_ACLK => S_AXI_ACLK,
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S_AXI_ARESETN => S_AXI_ARESETN,
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S_AXI_AWADDR => S_AXI_AWADDR,
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S_AXI_AWVALID => S_AXI_AWVALID,
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S_AXI_WDATA => S_AXI_WDATA,
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S_AXI_WSTRB => S_AXI_WSTRB,
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S_AXI_WVALID => S_AXI_WVALID,
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S_AXI_BREADY => S_AXI_BREADY,
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S_AXI_ARADDR => S_AXI_ARADDR,
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S_AXI_ARVALID => S_AXI_ARVALID,
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S_AXI_RREADY => S_AXI_RREADY,
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S_AXI_ARREADY => S_AXI_ARREADY,
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S_AXI_RDATA => S_AXI_RDATA,
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S_AXI_RRESP => S_AXI_RRESP,
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S_AXI_RVALID => S_AXI_RVALID,
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S_AXI_WREADY => S_AXI_WREADY,
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S_AXI_BRESP => S_AXI_BRESP,
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S_AXI_BVALID => S_AXI_BVALID,
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S_AXI_AWREADY => S_AXI_AWREADY,
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rd_addr => rd_addr,
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rd_data => rd_data,
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rd_ack => rd_ack,
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rd_stb => const_1,
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wr_addr => wr_addr,
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wr_data => wr_data,
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wr_ack => const_1,
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wr_stb => wr_stb
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);
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process(rd_addr, I2S_CONTROL_REG, I2S_CLK_CONTROL_REG, PERIOD_LEN_REG, rx_sample, cnt)
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begin
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case rd_addr is
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when 1 => rd_data <= I2S_CONTROL_REG and x"00000003";
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when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff";
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when 6 => rd_data <= PERIOD_LEN_REG and x"0000ffff";
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when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8));
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when others => rd_data <= (others => '0');
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end case;
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end process;
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process(S_AXI_ACLK) is
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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I2S_RESET_REG <= (others => '0');
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I2S_CONTROL_REG <= (others => '0');
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I2S_CLK_CONTROL_REG <= (others => '0');
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PERIOD_LEN_REG <= (others => '0');
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else
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-- Auto-clear the Reset Register bits
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I2S_RESET_REG(0) <= '0';
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I2S_RESET_REG(1) <= '0';
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I2S_RESET_REG(2) <= '0';
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if wr_stb = '1' then
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case wr_addr is
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when 0 => I2S_RESET_REG <= wr_data;
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when 1 => I2S_CONTROL_REG <= wr_data;
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when 2 => I2S_CLK_CONTROL_REG <= wr_data;
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when 6 => PERIOD_LEN_REG <= wr_data;
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when others => null;
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end case;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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