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AndreiGrozav 03e744f0f1 daq1_zed: Lower the adc and daq clock to 450MHz 
The FPGA fabric on zedboard is a -1 speadgrade (max bufg clk 464MHz)
 		2017-10-04 13:01:14 +01:00
..
Makefile hdlmake.pl updates 2017-07-31 09:02:12 -04:00
system_bd.tcl daq1_zed: Initial commit 2017-07-31 14:26:23 +03:00
system_constr.xdc daq1_zed: Lower the adc and daq clock to 450MHz 2017-10-04 13:01:14 +01:00
system_project.tcl daq1_zed: Initial commit 2017-07-31 14:26:23 +03:00
system_top.v daq1_zed: Initial commit 2017-07-31 14:26:23 +03:00