Lars-Peter Clausen f0655e63a6 avl_adxcvr: Derive PLL and core clock frequency from lane rate ... The PLL frequency must be half of the lane rate and the core clock rate must be lane rate divided by 40. There is no other option, otherwise things wont work. Instead of having to manually specify PLL and core clock frequency derive them in the transceiver script. This reduces the risk of accidental misconfiguration. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-07-28 15:11:08 +02:00
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fmcjesdadc1_bd.tcl	Connect JESD204 interrupts	2017-07-05 14:37:50 +02:00
fmcjesdadc1_qsys.tcl	avl_adxcvr: Derive PLL and core clock frequency from lane rate	2017-07-28 15:11:08 +02:00
fmcjesdadc1_spi.v	license: Add some clarification to the header license	2017-05-31 18:18:56 +03:00