119 lines
2.9 KiB
Verilog
119 lines
2.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module rx_lane_tb;
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parameter VCD_FILE = "rx_lane_tb.vcd";
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`include "tb_base.v"
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reg [31:0] data = {4{{3'd5,5'd28}}};
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reg [3:0] disperr = 4'b0000;
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reg [3:0] notintable = 4'b0000;
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reg [3:0] charisk = 4'b1111;
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wire ilas_config_valid;
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wire [1:0] ilas_config_addr;
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wire [4*8-1:0] ilas_config_data;
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wire [31:0] status_err_statistics_cnt;
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wire [4*8-1:0] rx_data;
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wire [1:0] status_cgs_state;
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wire status_ifs_ready;
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wire [2:0] status_frame_align;
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integer counter = 'h00;
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wire [31:0] counter2 = (counter - 'h20) * 4;
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always @(posedge clk) begin
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if ($urandom % 400 == 0)
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disperr <= 4'b1111;
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else if ($urandom % 400 == 1)
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disperr <= 4'b0001;
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else if ($urandom % 400 == 2)
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disperr <= 4'b0011;
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else if ($urandom % 400 == 3)
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disperr <= 4'b0111;
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else
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disperr <= 4'b0000;
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end
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always @(posedge clk) begin
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if ($random % 500 == 0)
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notintable <= 4'b1111;
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else
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notintable <= 4'b0000;
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end
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always @(posedge clk) begin
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counter <= counter + 1;
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if (counter == 'h20) begin
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charisk <= 'h0001;
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data[31:8] <= {{24'h020100}};
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end else if (counter == 'h21) begin
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charisk <= 'h0000;
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data[31:0] <= {{32'h06050403}};
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end else if (counter > 'h21) begin
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data <= (counter2 + 'h2) << 24 |
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(counter2 + 'h1) << 16 |
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(counter2 + 'h0) << 8 |
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(counter2 - 'h1);
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charisk <= 4'b0000;
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end
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end
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reg buffer_release_n = 1'b0;
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wire buffer_ready_n;
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always @(posedge clk) begin
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buffer_release_n <= buffer_ready_n;
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end
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jesd204_rx_lane i_rx_lane (
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.clk(clk),
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.reset(1'b0),
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.device_clk(clk),
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.device_reset(1'b0),
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.phy_data(data),
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.phy_charisk(charisk),
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.phy_disperr(disperr),
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.phy_notintable(notintable),
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.cgs_reset(reset),
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.cgs_ready(),
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.ifs_reset(1'b0),
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.rx_data(rx_data),
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.buffer_release_n(buffer_release_n),
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.buffer_ready_n(buffer_ready_n),
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.cfg_octets_per_multiframe(10'd31),
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.cfg_octets_per_frame(8'd3),
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.cfg_disable_char_replacement(1'b0),
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.cfg_disable_scrambler(1'b0),
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.ilas_config_valid(ilas_config_valid),
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.ilas_config_addr(ilas_config_addr),
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.ilas_config_data(ilas_config_data),
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.err_statistics_reset(1'b0),
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.ctrl_err_statistics_mask(3'h7),
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.status_err_statistics_cnt(status_err_statistics_cnt),
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.status_cgs_state(status_cgs_state),
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.status_ifs_ready(status_ifs_ready),
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.status_frame_align(status_frame_align),
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.status_frame_align_err_cnt());
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endmodule
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