98 lines
3.5 KiB
Tcl
98 lines
3.5 KiB
Tcl
###############################################################################
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## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad713x_di
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create_bd_port -dir O ad713x_odr
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create_bd_port -dir O ad713x_sdpclk
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# create a SPI Engine architecture for the parallel data interface of AD713x
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# this design supports AD7132/AD7134/AD7136
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
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set data_width 32
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set async_spi_clk 1
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set num_cs 1
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set num_sdi 8
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set num_sdo 0
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set sdi_delay 0
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set echo_sclk 0
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set hier_spi_engine dual_ad7134
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spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
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# clkgen
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ad_ip_instance axi_clkgen axi_ad7134_clkgen
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ad_ip_parameter axi_ad7134_clkgen CONFIG.VCO_DIV 5
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ad_ip_parameter axi_ad7134_clkgen CONFIG.VCO_MUL 48
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ad_ip_parameter axi_ad7134_clkgen CONFIG.CLK0_DIV 10
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# dma to receive data stream
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ad_ip_instance axi_dmac axi_ad7134_dma
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad7134_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad7134_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_SRC 256
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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# odr generator
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ad_ip_instance axi_pwm_gen odr_generator
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ad_ip_parameter odr_generator CONFIG.N_PWMS 2
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ad_ip_parameter odr_generator CONFIG.PULSE_0_PERIOD 85
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ad_ip_parameter odr_generator CONFIG.PULSE_0_WIDTH 1
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ad_ip_parameter odr_generator CONFIG.PULSE_0_OFFSET 3
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ad_ip_parameter odr_generator CONFIG.PULSE_1_PERIOD 85
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ad_ip_parameter odr_generator CONFIG.PULSE_1_WIDTH 13
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ad_connect odr_generator/ext_clk axi_ad7134_clkgen/clk_0
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ad_connect odr_generator/pwm_0 $hier_spi_engine/trigger
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ad_connect odr_generator/pwm_1 ad713x_odr
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# sdpclk clock generator - default clk0_out is 50 MHz
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ad_ip_instance axi_clkgen axi_sdp_clkgen
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ad_ip_parameter axi_sdp_clkgen CONFIG.CLKIN_PERIOD 10
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ad_ip_parameter axi_sdp_clkgen CONFIG.VCO_MUL 12
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ad_ip_parameter axi_sdp_clkgen CONFIG.VCO_DIV 2
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ad_ip_parameter axi_sdp_clkgen CONFIG.CLK0_DIV 12
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ad_connect axi_ad7134_clkgen/clk_0 $hier_spi_engine/spi_clk
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ad_connect $sys_cpu_clk axi_ad7134_clkgen/clk
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ad_connect $sys_cpu_clk $hier_spi_engine/clk
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ad_connect axi_ad7134_clkgen/clk_0 axi_ad7134_dma/s_axis_aclk
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ad_connect $sys_cpu_clk axi_sdp_clkgen/clk
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ad_connect sys_cpu_resetn $hier_spi_engine/resetn
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ad_connect sys_cpu_resetn axi_ad7134_dma/m_dest_axi_aresetn
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ad_connect $hier_spi_engine/m_spi ad713x_di
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ad_connect axi_ad7134_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE
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ad_connect ad713x_sdpclk axi_sdp_clkgen/clk_0
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# AXI address definitions
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ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
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ad_cpu_interconnect 0x44a30000 axi_ad7134_dma
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ad_cpu_interconnect 0x44a40000 axi_sdp_clkgen
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ad_cpu_interconnect 0x44b00000 odr_generator
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ad_cpu_interconnect 0x44b10000 axi_ad7134_clkgen
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# interrupts
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ad_cpu_interrupt "ps-13" "mb-13" axi_ad7134_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq
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# memory interconnects
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad7134_dma/m_dest_axi
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