302 lines
8.6 KiB
Verilog
Executable File
302 lines
8.6 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input sys_rst,
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input sys_clk_p,
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input sys_clk_n,
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input uart_sin,
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output uart_sout,
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output ddr4_act_n,
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output [16:0] ddr4_addr,
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output [ 1:0] ddr4_ba,
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output ddr4_bg,
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output ddr4_ck_p,
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output ddr4_ck_n,
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output ddr4_cke,
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output ddr4_cs_n,
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inout [ 7:0] ddr4_dm_n,
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inout [63:0] ddr4_dq,
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inout [ 7:0] ddr4_dqs_p,
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inout [ 7:0] ddr4_dqs_n,
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output ddr4_odt,
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output ddr4_reset_n,
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output mdio_mdc,
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inout mdio_mdio,
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input phy_clk_p,
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input phy_clk_n,
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output phy_rst_n,
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input phy_rx_p,
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input phy_rx_n,
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output phy_tx_p,
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output phy_tx_n,
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inout [16:0] gpio_bd,
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output iic_rstn,
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inout iic_scl,
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inout iic_sda,
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// FMC+ IOs
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input rx_ref_clk_p,
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input rx_ref_clk_n,
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input rx_ref_clk_replica_p,
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input rx_ref_clk_replica_n,
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input [15:0] rx_data_p,
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input [15:0] rx_data_n,
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input glbl_clk_0_p,
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input glbl_clk_0_n,
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input rx_sysref_p,
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input rx_sysref_n,
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output rx_sync_p,
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output rx_sync_n,
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output fpga_sclk,
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inout fpga_sdio,
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output fpga_csb,
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output adf4371_csb,
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output hmc7044_sclk,
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inout hmc7044_sdio,
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output hmc7044_csb,
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inout [ 4:0] gpio,
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output rstb,
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output hmc_sync_req
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);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire spi_miso;
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wire spi_mosi;
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wire hmc7044_miso;
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wire hmc7044_mosi;
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wire [ 1:0] hmc7044_csn;
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wire rx_ref_clk;
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wire rx_ref_clk_replica;
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wire rx_sysref;
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wire rx_sync;
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assign iic_rstn = 1'b1;
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assign hmc7044_csb = hmc7044_csn[0];
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assign adf4371_csb = hmc7044_csn[1];
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// instantiations
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IBUFDS_GTE4 i_ibufds_rx_ref_clk (
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.CEB (1'd0),
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.I (rx_ref_clk_p),
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.IB (rx_ref_clk_n),
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.O (rx_ref_clk),
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.ODIV2 ());
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IBUFDS_GTE4 i_ibufds_rx_ref_clk_replica (
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.CEB (1'd0),
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.I (rx_ref_clk_replica_p),
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.IB (rx_ref_clk_replica_n),
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.O (rx_ref_clk_replica),
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.ODIV2 ());
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IBUFDS i_ibufds_rx_sysref (
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.I (rx_sysref_p),
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.IB (rx_sysref_n),
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.O (rx_sysref));
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OBUFDS i_obufds_rx_sync (
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.I (rx_sync),
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.O (rx_sync_p),
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.OB (rx_sync_n));
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IBUFDS_GTE4 i_ibufds_glbl_clk_0 (
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.I (glbl_clk_0_p),
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.IB (glbl_clk_0_n),
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.ODIV2 (glbl_clk_0));
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BUFG_GT i_bufg_glbl_clk_0(
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.I (glbl_clk_0),
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.O (glbl_clk_buf));
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ad_iobuf #(
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.DATA_WIDTH(5)
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) i_iobuf (
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.dio_t (gpio_t[36:32]),
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.dio_i (gpio_o[36:32]),
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.dio_o (gpio_i[36:32]),
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.dio_p ({gpio[4:0]})); // 36-32
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assign hmc_sync_req = gpio_o[37];
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assign rstb = gpio_o[38];
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ad_iobuf #(
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.DATA_WIDTH(17)
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) i_iobuf_bd (
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.dio_t (gpio_t[16:0]),
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.dio_i (gpio_o[16:0]),
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.dio_o (gpio_i[16:0]),
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.dio_p (gpio_bd));
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assign gpio_i[63:38] = gpio_o[63:38];
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assign gpio_i[31:17] = gpio_o[31:17];
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ad_3w_spi #(
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.NUM_OF_SLAVES(2)
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) i_hmc7044_spi (
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.spi_csn (hmc7044_csn[1:0]),
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.spi_clk (hmc7044_sclk),
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.spi_mosi (hmc7044_mosi),
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.spi_miso (hmc7044_miso),
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.spi_sdio (hmc7044_sdio),
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.spi_dir ());
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ad_3w_spi #(
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.NUM_OF_SLAVES(1)
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) i_ad9213_spi (
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.spi_csn (fpga_csb),
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.spi_clk (fpga_sclk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_sdio (fpga_sdio),
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.spi_dir ());
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system_wrapper i_system_wrapper (
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.sys_rst (sys_rst),
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.sys_clk_clk_n (sys_clk_n),
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.sys_clk_clk_p (sys_clk_p),
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.ddr4_act_n (ddr4_act_n),
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.ddr4_adr (ddr4_addr),
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.ddr4_ba (ddr4_ba),
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.ddr4_bg (ddr4_bg),
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.ddr4_ck_c (ddr4_ck_n),
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.ddr4_ck_t (ddr4_ck_p),
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.ddr4_cke (ddr4_cke),
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.ddr4_cs_n (ddr4_cs_n),
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.ddr4_dm_n (ddr4_dm_n),
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.ddr4_dq (ddr4_dq),
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.ddr4_dqs_c (ddr4_dqs_n),
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.ddr4_dqs_t (ddr4_dqs_p),
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.ddr4_odt (ddr4_odt),
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.ddr4_reset_n (ddr4_reset_n),
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.phy_sd (1'b1),
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.phy_rst_n (phy_rst_n),
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.sgmii_rxn (phy_rx_n),
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.sgmii_rxp (phy_rx_p),
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.sgmii_txn (phy_tx_n),
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.sgmii_txp (phy_tx_p),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio),
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.sgmii_phyclk_clk_n (phy_clk_n),
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.sgmii_phyclk_clk_p (phy_clk_p),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout),
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.spi_clk_i (fpga_sclk),
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.spi_clk_o (fpga_sclk),
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.spi_csn_i (fpga_csb),
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.spi_csn_o (fpga_csb),
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.spi_sdi_i (spi_miso),
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.spi_sdo_i (spi_mosi),
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.spi_sdo_o (spi_mosi),
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.hmc7044_clk_i (hmc7044_sclk),
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.hmc7044_clk_o (hmc7044_sclk),
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.hmc7044_csn_i (hmc7044_csn),
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.hmc7044_csn_o (hmc7044_csn),
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.hmc7044_sdi_i (hmc7044_miso),
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.hmc7044_sdo_i (hmc7044_mosi),
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.hmc7044_sdo_o (hmc7044_mosi),
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.gpio0_i (gpio_i[31:0]),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio1_i (gpio_i[63:32]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]),
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// FMC+
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.rx_data_0_n (rx_data_n[1]),
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.rx_data_0_p (rx_data_p[1]),
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.rx_data_1_n (rx_data_n[3]),
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.rx_data_1_p (rx_data_p[3]),
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.rx_data_2_n (rx_data_n[2]),
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.rx_data_2_p (rx_data_p[2]),
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.rx_data_3_n (rx_data_n[4]),
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.rx_data_3_p (rx_data_p[4]),
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.rx_data_4_n (rx_data_n[0]),
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.rx_data_4_p (rx_data_p[0]),
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.rx_data_5_n (rx_data_n[15]),
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.rx_data_5_p (rx_data_p[15]),
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.rx_data_6_n (rx_data_n[8]),
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.rx_data_6_p (rx_data_p[8]),
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.rx_data_7_n (rx_data_n[7]),
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.rx_data_7_p (rx_data_p[7]),
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.rx_data_8_n (rx_data_n[5]),
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.rx_data_8_p (rx_data_p[5]),
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.rx_data_9_n (rx_data_n[6]),
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.rx_data_9_p (rx_data_p[6]),
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.rx_data_10_n (rx_data_n[10]),
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.rx_data_10_p (rx_data_p[10]),
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.rx_data_11_n (rx_data_n[9]),
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.rx_data_11_p (rx_data_p[9]),
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.rx_data_12_n (rx_data_n[12]),
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.rx_data_12_p (rx_data_p[12]),
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.rx_data_13_n (rx_data_n[14]),
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.rx_data_13_p (rx_data_p[14]),
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.rx_data_14_n (rx_data_n[13]),
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.rx_data_14_p (rx_data_p[13]),
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.rx_data_15_n (rx_data_n[11]),
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.rx_data_15_p (rx_data_p[11]),
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.rx_ref_clk_0 (rx_ref_clk),
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.rx_ref_clk_1 (rx_ref_clk_replica),
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.glbl_clk_0 (glbl_clk_buf),
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.rx_sync_0 (rx_sync),
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.rx_sysref_0 (rx_sysref));
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endmodule
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