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Istvan Csomortani bfa17844ff ad_serdes_in: General update 
Added a parameter for option SDR / DDR mode, added a parameter for parallel data width.
Note: default IF_TYPE is SDR and default PARALLEL_WIDTH is 8
 		2014-10-07 17:42:27 +03:00
library ad_serdes_in: General update 2014-10-07 17:42:27 +03:00
projects projects/common/xxx/xxx_system_bd.tcl: 'Update microblaze defaults 2014-10-07 09:17:24 +02:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Add a link to EngineerZone 2014-04-15 10:25:18 +03:00

README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga