bfcc3696e4
Depending on the configuration of the clock source type of the input clock the clocking wizard will instantiate all kinds of buffers on the input clock signal. For these particular projects there is no need to add any kind of buffer since the source is already coming from a global clock buffer. So set the configuration accordingly. Avoids the following warning: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. i_system_wrapper/system_i/sys_audio_clkgen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects
Branches
Each release has its own branch and master always synced with the latest release. To find out more information about the latest release please check the release notes. Every branch, which has dev in its name, is a development branch and should handle it accordingly.