270 lines
7.5 KiB
Verilog
270 lines
7.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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ddr_addr,
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ddr_ba,
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ddr_cas_n,
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ddr_ck_n,
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ddr_ck_p,
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ddr_cke,
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ddr_cs_n,
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ddr_dm,
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ddr_dq,
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ddr_dqs_n,
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ddr_dqs_p,
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ddr_odt,
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ddr_ras_n,
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ddr_reset_n,
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ddr_we_n,
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fixed_io_ddr_vrn,
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fixed_io_ddr_vrp,
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fixed_io_mio,
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fixed_io_ps_clk,
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fixed_io_ps_porb,
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fixed_io_ps_srstb,
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gpio_bd,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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spdif,
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iic_scl,
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iic_sda,
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rx_ref_clk_p,
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rx_ref_clk_n,
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rx_sysref,
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rx_sync,
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rx_data_p,
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rx_data_n,
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spi_csn,
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spi_clk,
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spi_sdio);
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inout [14:0] ddr_addr;
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inout [ 2:0] ddr_ba;
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inout ddr_cas_n;
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inout ddr_ck_n;
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inout ddr_ck_p;
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inout ddr_cke;
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inout ddr_cs_n;
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inout [ 3:0] ddr_dm;
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inout [31:0] ddr_dq;
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inout [ 3:0] ddr_dqs_n;
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inout [ 3:0] ddr_dqs_p;
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inout ddr_odt;
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inout ddr_ras_n;
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inout ddr_reset_n;
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inout ddr_we_n;
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inout fixed_io_ddr_vrn;
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inout fixed_io_ddr_vrp;
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inout [53:0] fixed_io_mio;
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inout fixed_io_ps_clk;
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inout fixed_io_ps_porb;
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inout fixed_io_ps_srstb;
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inout [14:0] gpio_bd;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [23:0] hdmi_data;
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output spdif;
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inout iic_scl;
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inout iic_sda;
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input rx_ref_clk_p;
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input rx_ref_clk_n;
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output rx_sysref;
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output rx_sync;
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input [ 3:0] rx_data_p;
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input [ 3:0] rx_data_n;
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output spi_csn;
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output spi_clk;
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inout spi_sdio;
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire rx_ref_clk;
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wire [ 2:0] spi0_csn;
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wire spi0_clk;
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wire spi0_mosi;
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wire spi0_miso;
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wire [ 2:0] spi1_csn;
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wire spi1_clk;
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wire spi1_mosi;
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wire spi1_miso;
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wire rx_clk;
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wire rx_sysref;
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assign spi_csn = spi0_csn[0];
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assign spi_clk = spi0_clk;
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assign spi_mosi = spi0_mosi;
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assign spi0_miso = spi_miso;
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// instantiations
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IBUFDS_GTE2 i_ibufds_rx_ref_clk (
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.CEB (1'd0),
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.I (rx_ref_clk_p),
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.IB (rx_ref_clk_n),
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.O (rx_ref_clk),
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.ODIV2 ());
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ad_iobuf #(.DATA_WIDTH(15)) i_iobuf (
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.dio_t (gpio_t[14:0]),
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.dio_i (gpio_o[14:0]),
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.dio_o (gpio_i[14:0]),
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.dio_p (gpio_bd));
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assign spi_adc_clk = spi_clk;
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assign spi_clk_clk = spi_clk;
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fmcjesdadc1_spi i_fmcjesdadc1_spi (
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.spi_csn (spi_csn),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_sdio (spi_sdio));
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ad_sysref_gen i_sysref (
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.core_clk (rx_clk),
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.sysref_en (gpio_o[32]),
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.sysref_out (rx_sysref));
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.ps_intr_00 (1'b0),
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.ps_intr_01 (1'b0),
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.ps_intr_02 (1'b0),
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.ps_intr_03 (1'b0),
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.ps_intr_04 (1'b0),
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.ps_intr_05 (1'b0),
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.ps_intr_06 (1'b0),
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.ps_intr_07 (1'b0),
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.ps_intr_08 (1'b0),
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.ps_intr_09 (1'b0),
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.ps_intr_10 (1'b0),
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.ps_intr_11 (1'b0),
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.rx_data_0_n (rx_data_n[0]),
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.rx_data_0_p (rx_data_p[0]),
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.rx_data_1_n (rx_data_n[1]),
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.rx_data_1_p (rx_data_p[1]),
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.rx_data_2_n (rx_data_n[2]),
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.rx_data_2_p (rx_data_p[2]),
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.rx_data_3_n (rx_data_n[3]),
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.rx_data_3_p (rx_data_p[3]),
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.rx_ref_clk_0 (rx_ref_clk),
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.rx_sync_0 (rx_sync),
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.rx_sysref_0 (rx_sysref),
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.rx_core_clk (rx_clk),
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.spdif (spdif),
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.spi0_clk_i (spi0_clk),
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.spi0_clk_o (spi0_clk),
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.spi0_csn_0_o (spi0_csn[0]),
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.spi0_csn_1_o (spi0_csn[1]),
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.spi0_csn_2_o (spi0_csn[2]),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (spi0_miso),
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.spi0_sdo_i (spi0_mosi),
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.spi0_sdo_o (spi0_mosi),
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.spi1_clk_i (spi1_clk),
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.spi1_clk_o (spi1_clk),
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.spi1_csn_0_o (spi1_csn[0]),
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.spi1_csn_1_o (spi1_csn[1]),
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.spi1_csn_2_o (spi1_csn[2]),
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.spi1_csn_i (1'b1),
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.spi1_sdi_i (1'b1),
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.spi1_sdo_i (spi1_mosi),
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.spi1_sdo_o (spi1_mosi));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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