302 lines
9.3 KiB
Verilog
302 lines
9.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_laser_driver #(
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parameter ID = 0,
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parameter [0:0] ASYNC_CLK_EN = 1,
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parameter PULSE_WIDTH = 7,
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parameter PULSE_PERIOD = 10 )(
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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// external clock and control/status signals
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input ext_clk,
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output driver_en_n,
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output driver_pulse,
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input driver_otw_n,
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output driver_dp_reset,
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output reg [ 7:0] tia_chsel,
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// interrupt
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output irq);
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// internal signals
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reg up_wack = 1'b0;
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reg up_rack = 1'b0;
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reg [31:0] up_rdata = 32'b0;
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reg driver_pulse_int_d = 1'b0;
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reg [ 1:0] sequence_counter = 2'b00;
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// internal signals
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wire clk;
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wire up_clk;
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wire up_rstn;
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wire up_rreq_s;
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wire up_rack_ld_s;
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wire up_rack_pwm_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_ld_s;
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wire [31:0] up_rdata_pwm_s;
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wire up_wreq_s;
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wire up_wack_ld_s;
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wire up_wack_pwm_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] pulse_width_s;
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wire [31:0] pulse_period_s;
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wire load_config_s;
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wire pulse_gen_resetn;
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wire [31:0] pulse_counter_s;
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wire driver_pulse_int_s;
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wire [31:0] up_ext_clk_count_s;
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wire sequence_en_s;
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wire auto_sequence_s;
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wire [31:0] sequence_offset_s;
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wire [ 1:0] auto_seq0_s;
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wire [ 1:0] auto_seq1_s;
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wire [ 1:0] auto_seq2_s;
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wire [ 1:0] auto_seq3_s;
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wire [ 7:0] manual_select_s;
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// local parameters
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localparam [31:0] CORE_VERSION = {16'h0001, /* MAJOR */
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8'h00, /* MINOR */
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8'h61}; /* PATCH */ // 1.00.a
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localparam [31:0] CORE_MAGIC = 32'h4C534452; // LSDR
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// register maps
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axi_pulse_gen_regmap #(
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.ID (ID),
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.CORE_MAGIC (CORE_MAGIC),
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.CORE_VERSION (CORE_VERSION),
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.ASYNC_CLK_EN (ASYNC_CLK_EN),
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.PULSE_WIDTH (PULSE_WIDTH),
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.PULSE_PERIOD (PULSE_PERIOD))
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i_pwm_regmap (
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.ext_clk (ext_clk),
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.clk_out (clk),
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.pulse_gen_resetn (pulse_gen_resetn),
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.pulse_width (pulse_width_s),
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.pulse_period (pulse_period_s),
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.load_config (load_config_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_pwm_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_pwm_s),
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.up_rack (up_rack_pwm_s));
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axi_laser_driver_regmap #(
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.ID (ID),
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.LASER_DRIVER_ID (1))
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i_laser_driver_regmap (
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.clk (clk),
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.driver_en_n (driver_en_n),
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.driver_otw_n (driver_otw_n),
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.pulse (driver_pulse_int_s),
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.up_ext_clk_count (up_ext_clk_count_s),
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.irq (irq),
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.sequence_en (sequence_en_s),
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.auto_sequence (auto_sequence_s),
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.sequence_offset (sequence_offset_s),
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.auto_seq0 (auto_seq0_s),
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.auto_seq1 (auto_seq1_s),
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.auto_seq2 (auto_seq2_s),
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.auto_seq3 (auto_seq3_s),
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.manual_select (manual_select_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_ld_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_ld_s),
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.up_rack (up_rack_ld_s));
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// read interface merge
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_wack <= up_wack_ld_s | up_wack_pwm_s;
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up_rack <= up_rack_ld_s | up_rack_pwm_s;
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up_rdata <= up_rdata_ld_s | up_rdata_pwm_s;
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end
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end
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// generic PWM generator's
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util_pulse_gen #(
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.PULSE_WIDTH(PULSE_WIDTH),
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.PULSE_PERIOD(PULSE_PERIOD))
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i_laser_driver_pulse (
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.clk (clk),
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.rstn (pulse_gen_resetn),
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.pulse_width (pulse_width_s),
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.pulse_period (pulse_period_s),
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.load_config (load_config_s),
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.pulse (driver_pulse_int_s),
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.pulse_counter (pulse_counter_s));
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// data path reset generation
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// this logic will generate a reset signal right before the generated pulse
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// in order to use it for resetting the cpack module, to synchronize it to
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// the driver pulse
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always @(posedge clk) begin
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driver_pulse_int_d <= driver_pulse_int_s;
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end
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assign driver_dp_reset = driver_pulse_int_s & ~driver_pulse_int_d;
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assign driver_pulse = driver_pulse_int_d;
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// clock monitor for the external clock
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up_clock_mon i_clock_mon (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_d_count (up_ext_clk_count_s),
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.d_rst (~pulse_gen_resetn),
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.d_clk (ext_clk));
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// TIA sequencer
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always @(posedge clk) begin
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if (sequence_en_s == 1'b0) begin
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sequence_counter <= 2'b00;
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end else begin
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if (pulse_counter_s == sequence_offset_s) begin
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if (auto_sequence_s) begin
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sequence_counter <= sequence_counter + 1'b1;
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end
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end
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end
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end
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always @(posedge clk) begin
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if (sequence_en_s == 1'b0) begin
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tia_chsel <= 8'h00;
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end else begin
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if (pulse_counter_s == sequence_offset_s) begin
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if (auto_sequence_s) begin
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case (sequence_counter)
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2'b00 : tia_chsel <= {auto_seq0_s, auto_seq0_s, auto_seq0_s, auto_seq0_s};
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2'b01 : tia_chsel <= {auto_seq1_s, auto_seq1_s, auto_seq1_s, auto_seq1_s};
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2'b10 : tia_chsel <= {auto_seq2_s, auto_seq2_s, auto_seq2_s, auto_seq2_s};
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2'b11 : tia_chsel <= {auto_seq3_s, auto_seq3_s, auto_seq3_s, auto_seq3_s};
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default : tia_chsel <= 8'h00;
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endcase
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end else begin
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tia_chsel <= manual_select_s;
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end
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end
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end
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end
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// AXI Memory Mapped Wrapper
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up_axi #(
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.AXI_ADDRESS_WIDTH(16))
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i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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