72 lines
2.6 KiB
Tcl
72 lines
2.6 KiB
Tcl
proc spi_engine_create {{name "hier_spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {sdi_delay 2}} {
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create_bd_cell -type hier $name
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current_bd_instance /$name
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if {$async_spi_clk == 1} {
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create_bd_pin -dir I -type clk spi_clk
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}
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir I trigger
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_sample
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ad_ip_instance spi_engine_execution execution
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ad_ip_parameter execution CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter execution CONFIG.NUM_OF_CS $num_cs
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ad_ip_parameter execution CONFIG.NUM_OF_SDI $num_sdi
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ad_ip_parameter execution CONFIG.SDO_DEFAULT 1
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ad_ip_parameter execution CONFIG.SDI_DELAY $sdi_delay
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ad_ip_instance axi_spi_engine axi_regmap
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ad_ip_parameter axi_regmap CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter axi_regmap CONFIG.NUM_OFFLOAD 1
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ad_ip_parameter axi_regmap CONFIG.NUM_OF_SDI $num_sdi
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ad_ip_parameter axi_regmap CONFIG.ASYNC_SPI_CLK $async_spi_clk
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ad_ip_instance spi_engine_offload offload
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ad_ip_parameter offload CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter offload CONFIG.ASYNC_SPI_CLK $async_spi_clk
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ad_ip_parameter offload CONFIG.NUM_OF_SDI $num_sdi
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ad_ip_instance spi_engine_interconnect interconnect
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ad_ip_parameter interconnect CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter interconnect CONFIG.NUM_OF_SDI $num_sdi
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ad_connect axi_regmap/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi_regmap/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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ad_connect offload/offload_sdi m_axis_sample
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ad_connect offload/trigger trigger
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ad_connect execution/spi m_spi
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ad_connect clk axi_regmap/s_axi_aclk
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if {$async_spi_clk == 1} {
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ad_connect spi_clk offload/spi_clk
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ad_connect spi_clk offload/ctrl_clk
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ad_connect spi_clk execution/clk
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ad_connect spi_clk axi_regmap/spi_clk
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ad_connect spi_clk interconnect/clk
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} else {
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ad_connect clk offload/spi_clk
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ad_connect clk offload/ctrl_clk
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ad_connect clk execution/clk
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ad_connect clk axi_regmap/spi_clk
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ad_connect clk interconnect/clk
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}
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ad_connect axi_regmap/spi_resetn offload/spi_resetn
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ad_connect axi_regmap/spi_resetn execution/resetn
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ad_connect axi_regmap/spi_resetn interconnect/resetn
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ad_connect resetn axi_regmap/s_axi_aresetn
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ad_connect irq axi_regmap/irq
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current_bd_instance /
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}
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