pluto_hdl_adi/projects/fmcomms5
AndreiGrozav 235636a337 fmcomms5_zc702: Enable AXI_SLICE for the DMA
This will increase the timing margin for the design
2018-07-18 18:19:30 +03:00
..
common fmcomms5: Connect the DAC data underflow 2018-04-13 18:46:29 +03:00
zc702 fmcomms5_zc702: Enable AXI_SLICE for the DMA 2018-07-18 18:19:30 +03:00
zc706 fmcomms5: Delete unused GPIO lines from system top 2018-05-30 09:55:04 +03:00
zcu102 fmcomms5: Delete unused GPIO lines from system top 2018-05-30 09:55:04 +03:00
Makefile Regenerate project top-level Makefiles 2018-04-11 15:09:54 +03:00