pluto_hdl_adi/library/axi_ad9144/axi_ad9144_ip.tcl

39 lines
1.2 KiB
Tcl

# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_ad9144
adi_ip_files axi_ad9144 [list \
"axi_ad9144.v" ]
adi_ip_properties axi_ad9144
adi_init_bd_tcl
adi_ip_bd axi_ad9144 "bd/bd.tcl"
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9144} [ipx::current_core]
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:ad_ip_jesd204_tpl_dac:1.0 \
]
adi_set_ports_dependency "dac_valid_2" "QUAD_OR_DUAL_N == 1"
adi_set_ports_dependency "dac_valid_3" "QUAD_OR_DUAL_N == 1"
adi_set_ports_dependency "dac_enable_2" "QUAD_OR_DUAL_N == 1"
adi_set_ports_dependency "dac_enable_3" "QUAD_OR_DUAL_N == 1"
adi_set_ports_dependency "dac_ddata_2" "QUAD_OR_DUAL_N == 1" "0"
adi_set_ports_dependency "dac_ddata_3" "QUAD_OR_DUAL_N == 1" "0"
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]