496 lines
15 KiB
Verilog
496 lines
15 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adrv9001_if #(
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parameter CMOS_LVDS_N = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter NUM_LANES = 3,
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parameter DRP_WIDTH = 5,
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parameter RX_USE_BUFG = 0,
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parameter TX_USE_BUFG = 0,
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parameter DISABLE_RX2_SSI = 0,
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parameter DISABLE_TX2_SSI = 0,
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parameter IODELAY_CTRL = 1,
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parameter IO_DELAY_GROUP = "dev_if_delay_group",
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parameter USE_RX_CLK_FOR_TX = 0
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) (
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input ref_clk,
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input tx_output_enable,
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input mssi_sync,
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// device interface
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input rx1_dclk_in_n_NC,
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input rx1_dclk_in_p_dclk_in,
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input rx1_idata_in_n_idata0,
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input rx1_idata_in_p_idata1,
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input rx1_qdata_in_n_qdata2,
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input rx1_qdata_in_p_qdata3,
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input rx1_strobe_in_n_NC,
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input rx1_strobe_in_p_strobe_in,
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input rx2_dclk_in_n_NC,
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input rx2_dclk_in_p_dclk_in,
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input rx2_idata_in_n_idata0,
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input rx2_idata_in_p_idata1,
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input rx2_qdata_in_n_qdata2,
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input rx2_qdata_in_p_qdata3,
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input rx2_strobe_in_n_NC,
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input rx2_strobe_in_p_strobe_in,
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output tx1_dclk_out_n_NC,
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output tx1_dclk_out_p_dclk_out,
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input tx1_dclk_in_n_NC,
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input tx1_dclk_in_p_dclk_in,
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output tx1_idata_out_n_idata0,
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output tx1_idata_out_p_idata1,
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output tx1_qdata_out_n_qdata2,
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output tx1_qdata_out_p_qdata3,
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output tx1_strobe_out_n_NC,
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output tx1_strobe_out_p_strobe_out,
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output tx2_dclk_out_n_NC,
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output tx2_dclk_out_p_dclk_out,
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input tx2_dclk_in_n_NC,
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input tx2_dclk_in_p_dclk_in,
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output tx2_idata_out_n_idata0,
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output tx2_idata_out_p_idata1,
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output tx2_qdata_out_n_qdata2,
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output tx2_qdata_out_p_qdata3,
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output tx2_strobe_out_n_NC,
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output tx2_strobe_out_p_strobe_out,
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// delay interface (for IDELAY macros)
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input delay_clk,
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input delay_rx1_rst,
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input delay_rx2_rst,
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output delay_rx1_locked,
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output delay_rx2_locked,
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input up_clk,
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input [NUM_LANES-1:0] up_rx1_dld,
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input [DRP_WIDTH*NUM_LANES-1:0] up_rx1_dwdata,
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output [DRP_WIDTH*NUM_LANES-1:0] up_rx1_drdata,
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input [NUM_LANES-1:0] up_rx2_dld,
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input [DRP_WIDTH*NUM_LANES-1:0] up_rx2_dwdata,
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output [DRP_WIDTH*NUM_LANES-1:0] up_rx2_drdata,
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// upper layer data interface
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output [ 31:0] adc_clk_ratio,
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output [ 31:0] dac_clk_ratio,
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output rx1_clk,
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input rx1_rst,
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output rx1_data_valid,
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output [15:0] rx1_data_i,
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output [15:0] rx1_data_q,
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input rx1_single_lane,
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input rx1_sdr_ddr_n,
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input rx1_symb_op,
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input rx1_symb_8_16b,
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output rx2_clk,
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input rx2_rst,
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output rx2_data_valid,
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output [15:0] rx2_data_i,
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output [15:0] rx2_data_q,
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input rx2_single_lane,
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input rx2_sdr_ddr_n,
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input rx2_symb_op,
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input rx2_symb_8_16b,
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output tx1_clk,
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input tx1_rst,
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input tx1_data_valid,
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input [15:0] tx1_data_i,
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input [15:0] tx1_data_q,
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input tx1_single_lane,
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input tx1_sdr_ddr_n,
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input tx1_symb_op,
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input tx1_symb_8_16b,
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output tx2_clk,
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input tx2_rst,
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input tx2_data_valid,
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input [15:0] tx2_data_i,
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input [15:0] tx2_data_q,
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input tx2_single_lane,
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input tx2_sdr_ddr_n,
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input tx2_symb_op,
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input tx2_symb_8_16b
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);
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// Tx has an extra lane to drive the clock
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localparam TX_NUM_LANES = NUM_LANES + 1;
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wire adc_1_clk_div;
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wire [7:0] adc_1_data_0;
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wire [7:0] adc_1_data_1;
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wire [7:0] adc_1_data_2;
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wire [7:0] adc_1_data_3;
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wire [7:0] adc_1_data_strobe;
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wire adc_1_clk;
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wire adc_1_valid;
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wire adc_1_ssi_rst;
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wire adc_2_clk_div;
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wire [7:0] adc_2_data_0;
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wire [7:0] adc_2_data_1;
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wire [7:0] adc_2_data_2;
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wire [7:0] adc_2_data_3;
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wire [7:0] adc_2_data_strobe;
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wire adc_2_clk;
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wire adc_2_valid;
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wire adc_2_ssi_rst;
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wire dac_1_clk_div;
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wire [7:0] dac_1_data_0;
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wire [7:0] dac_1_data_1;
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wire [7:0] dac_1_data_2;
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wire [7:0] dac_1_data_3;
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wire [7:0] dac_1_data_strobe;
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wire [7:0] dac_1_data_clk;
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wire dac_1_data_valid;
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wire dac_2_clk_div;
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wire [7:0] dac_2_data_0;
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wire [7:0] dac_2_data_1;
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wire [7:0] dac_2_data_2;
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wire [7:0] dac_2_data_3;
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wire [7:0] dac_2_data_strobe;
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wire [7:0] dac_2_data_clk;
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wire dac_2_data_valid;
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wire rx_ssi_sync_out;
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adrv9001_rx
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#(.CMOS_LVDS_N (CMOS_LVDS_N),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.NUM_LANES (NUM_LANES),
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.DRP_WIDTH (DRP_WIDTH),
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.IODELAY_CTRL (IODELAY_CTRL),
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.USE_BUFG (RX_USE_BUFG),
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.IO_DELAY_GROUP ({IO_DELAY_GROUP,"_rx"})
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) i_rx_1_phy (
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.rx_dclk_in_n_NC (rx1_dclk_in_n_NC),
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.rx_dclk_in_p_dclk_in (rx1_dclk_in_p_dclk_in),
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.rx_idata_in_n_idata0 (rx1_idata_in_n_idata0),
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.rx_idata_in_p_idata1 (rx1_idata_in_p_idata1),
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.rx_qdata_in_n_qdata2 (rx1_qdata_in_n_qdata2),
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.rx_qdata_in_p_qdata3 (rx1_qdata_in_p_qdata3),
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.rx_strobe_in_n_NC (rx1_strobe_in_n_NC),
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.rx_strobe_in_p_strobe_in (rx1_strobe_in_p_strobe_in),
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.adc_rst (rx1_rst),
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.adc_clk (adc_1_clk),
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.adc_clk_div (adc_1_clk_div),
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.adc_data_0 (adc_1_data_0),
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.adc_data_1 (adc_1_data_1),
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.adc_data_2 (adc_1_data_2),
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.adc_data_3 (adc_1_data_3),
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.adc_data_strobe (adc_1_data_strobe),
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.adc_valid (adc_1_valid),
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.adc_clk_ratio (adc_clk_ratio),
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.up_clk (up_clk),
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.up_adc_dld (up_rx1_dld),
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.up_adc_dwdata (up_rx1_dwdata),
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.up_adc_drdata (up_rx1_drdata),
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.delay_clk (delay_clk),
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.delay_rst (delay_rx1_rst),
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.delay_locked (delay_rx1_locked),
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.mssi_sync (mssi_sync),
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.ssi_sync_out (rx_ssi_sync_out),
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.ssi_sync_in (rx_ssi_sync_out),
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.ssi_rst (adc_1_ssi_rst)
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);
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adrv9001_rx_link #(
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.CMOS_LVDS_N (CMOS_LVDS_N)
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) i_rx_1_link (
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.adc_rst (rx1_rst),
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.adc_clk_div (adc_1_clk_div),
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.adc_data_0 (adc_1_data_0),
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.adc_data_1 (adc_1_data_1),
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.adc_data_2 (adc_1_data_2),
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.adc_data_3 (adc_1_data_3),
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.adc_data_strobe (adc_1_data_strobe),
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.adc_valid (adc_1_valid),
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// ADC interface
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.rx_clk (rx1_clk),
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.rx_data_valid (rx1_data_valid),
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.rx_data_i (rx1_data_i),
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.rx_data_q (rx1_data_q),
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.rx_single_lane (rx1_single_lane),
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.rx_sdr_ddr_n (rx1_sdr_ddr_n),
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.rx_symb_op (rx1_symb_op),
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.rx_symb_8_16b (rx1_symb_8_16b)
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);
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generate if (DISABLE_RX2_SSI == 0) begin
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adrv9001_rx
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#(.CMOS_LVDS_N (CMOS_LVDS_N),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.NUM_LANES (NUM_LANES),
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.DRP_WIDTH (DRP_WIDTH),
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.IODELAY_CTRL (0),
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.USE_BUFG (RX_USE_BUFG),
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.IO_DELAY_GROUP ({IO_DELAY_GROUP,"_rx"})
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) i_rx_2_phy (
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.rx_dclk_in_n_NC (rx2_dclk_in_n_NC),
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.rx_dclk_in_p_dclk_in (rx2_dclk_in_p_dclk_in),
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.rx_idata_in_n_idata0 (rx2_idata_in_n_idata0),
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.rx_idata_in_p_idata1 (rx2_idata_in_p_idata1),
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.rx_qdata_in_n_qdata2 (rx2_qdata_in_n_qdata2),
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.rx_qdata_in_p_qdata3 (rx2_qdata_in_p_qdata3),
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.rx_strobe_in_n_NC (rx2_strobe_in_n_NC),
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.rx_strobe_in_p_strobe_in (rx2_strobe_in_p_strobe_in),
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.adc_rst (rx2_rst),
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.adc_clk (adc_2_clk),
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.adc_clk_div (adc_2_clk_div),
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.adc_data_0 (adc_2_data_0),
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.adc_data_1 (adc_2_data_1),
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.adc_data_2 (adc_2_data_2),
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.adc_data_3 (adc_2_data_3),
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.adc_data_strobe (adc_2_data_strobe),
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.adc_valid (adc_2_valid),
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.up_clk (up_clk),
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.up_adc_dld (up_rx2_dld),
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.up_adc_dwdata (up_rx2_dwdata),
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.up_adc_drdata (up_rx2_drdata),
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.delay_clk (delay_clk),
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.delay_rst (delay_rx2_rst),
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.delay_locked (delay_rx2_locked),
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.mssi_sync (1'b0),
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.ssi_sync_out (),
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.ssi_sync_in (rx_ssi_sync_out),
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.ssi_rst (adc_2_ssi_rst)
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);
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adrv9001_rx_link #(
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.CMOS_LVDS_N (CMOS_LVDS_N)
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) i_rx_2_link (
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.adc_rst (rx2_rst),
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.adc_clk_div (adc_2_clk_div),
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.adc_data_0 (adc_2_data_0),
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.adc_data_1 (adc_2_data_1),
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.adc_data_2 (adc_2_data_2),
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.adc_data_3 (adc_2_data_3),
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.adc_data_strobe (adc_2_data_strobe),
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.adc_valid (adc_2_valid),
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// ADC interface
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.rx_clk (rx2_clk),
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.rx_data_valid (rx2_data_valid),
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.rx_data_i (rx2_data_i),
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.rx_data_q (rx2_data_q),
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.rx_single_lane (rx2_single_lane),
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.rx_sdr_ddr_n (rx2_sdr_ddr_n),
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.rx_symb_op (rx2_symb_op),
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.rx_symb_8_16b (rx2_symb_8_16b)
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);
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end else begin
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assign delay_rx2_locked = 1'b1;
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assign up_rx2_drdata = 'h0;
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assign rx2_clk = 1'b0;
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assign rx2_data_valid = 1'b0;
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assign rx2_data_i = 16'b0;
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assign rx2_data_q = 16'b0;
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end
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endgenerate
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adrv9001_tx #(
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.CMOS_LVDS_N (CMOS_LVDS_N),
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.NUM_LANES (TX_NUM_LANES),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.USE_BUFG (TX_USE_BUFG),
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.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
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) i_tx_1_phy (
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.ref_clk (ref_clk),
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.up_clk (up_clk),
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.tx_output_enable(tx_output_enable),
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.tx_dclk_out_n_NC (tx1_dclk_out_n_NC),
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.tx_dclk_out_p_dclk_out (tx1_dclk_out_p_dclk_out),
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.tx_dclk_in_n_NC (tx1_dclk_in_n_NC),
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.tx_dclk_in_p_dclk_in (tx1_dclk_in_p_dclk_in),
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.tx_idata_out_n_idata0 (tx1_idata_out_n_idata0),
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.tx_idata_out_p_idata1 (tx1_idata_out_p_idata1),
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.tx_qdata_out_n_qdata2 (tx1_qdata_out_n_qdata2),
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.tx_qdata_out_p_qdata3 (tx1_qdata_out_p_qdata3),
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.tx_strobe_out_n_NC (tx1_strobe_out_n_NC),
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.tx_strobe_out_p_strobe_out (tx1_strobe_out_p_strobe_out),
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.rx_clk_div (adc_1_clk_div),
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.rx_clk (adc_1_clk),
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.rx_ssi_rst (adc_1_ssi_rst),
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.dac_rst (tx1_rst),
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.dac_clk_div (dac_1_clk_div),
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.dac_data_0 (dac_1_data_0),
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.dac_data_1 (dac_1_data_1),
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.dac_data_2 (dac_1_data_2),
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.dac_data_3 (dac_1_data_3),
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.dac_data_strb (dac_1_data_strobe),
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.dac_data_clk (dac_1_data_clk),
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.dac_data_valid (dac_1_data_valid),
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.dac_clk_ratio (dac_clk_ratio),
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.mssi_sync (mssi_sync)
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);
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adrv9001_tx_link #(
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.CMOS_LVDS_N (CMOS_LVDS_N),
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.CLK_DIV_IS_FAST_CLK (FPGA_TECHNOLOGY >= 100)
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) i_tx_1_link (
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.dac_clk_div (dac_1_clk_div),
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.dac_data_0 (dac_1_data_0),
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.dac_data_1 (dac_1_data_1),
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.dac_data_2 (dac_1_data_2),
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.dac_data_3 (dac_1_data_3),
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.dac_data_strobe (dac_1_data_strobe),
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.dac_data_clk (dac_1_data_clk),
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.dac_data_valid (dac_1_data_valid),
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// DAC interface
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.tx_clk (tx1_clk),
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.tx_rst (tx1_rst),
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.tx_data_valid (tx1_data_valid),
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.tx_data_i (tx1_data_i),
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.tx_data_q (tx1_data_q),
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.tx_sdr_ddr_n (tx1_sdr_ddr_n),
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.tx_single_lane (tx1_single_lane),
|
|
.tx_symb_op (tx1_symb_op),
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|
.tx_symb_8_16b (tx1_symb_8_16b)
|
|
);
|
|
|
|
generate if (DISABLE_TX2_SSI == 0) begin
|
|
adrv9001_tx #(
|
|
.CMOS_LVDS_N (CMOS_LVDS_N),
|
|
.NUM_LANES (TX_NUM_LANES),
|
|
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
|
.USE_BUFG (TX_USE_BUFG),
|
|
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
|
|
) i_tx_2_phy (
|
|
|
|
.ref_clk (ref_clk),
|
|
.up_clk (up_clk),
|
|
|
|
.tx_output_enable(tx_output_enable),
|
|
|
|
.tx_dclk_out_n_NC (tx2_dclk_out_n_NC),
|
|
.tx_dclk_out_p_dclk_out (tx2_dclk_out_p_dclk_out),
|
|
.tx_dclk_in_n_NC (tx2_dclk_in_n_NC),
|
|
.tx_dclk_in_p_dclk_in (tx2_dclk_in_p_dclk_in),
|
|
.tx_idata_out_n_idata0 (tx2_idata_out_n_idata0),
|
|
.tx_idata_out_p_idata1 (tx2_idata_out_p_idata1),
|
|
.tx_qdata_out_n_qdata2 (tx2_qdata_out_n_qdata2),
|
|
.tx_qdata_out_p_qdata3 (tx2_qdata_out_p_qdata3),
|
|
.tx_strobe_out_n_NC (tx2_strobe_out_n_NC),
|
|
.tx_strobe_out_p_strobe_out (tx2_strobe_out_p_strobe_out),
|
|
|
|
.rx_clk_div (adc_2_clk_div),
|
|
.rx_clk (adc_2_clk),
|
|
.rx_ssi_rst (adc_2_ssi_rst),
|
|
|
|
.dac_rst (tx2_rst),
|
|
.dac_clk_div (dac_2_clk_div),
|
|
|
|
.dac_data_0 (dac_2_data_0),
|
|
.dac_data_1 (dac_2_data_1),
|
|
.dac_data_2 (dac_2_data_2),
|
|
.dac_data_3 (dac_2_data_3),
|
|
.dac_data_strb (dac_2_data_strobe),
|
|
.dac_data_clk (dac_2_data_clk),
|
|
.dac_data_valid (dac_2_data_valid),
|
|
|
|
.mssi_sync (mssi_sync)
|
|
);
|
|
|
|
adrv9001_tx_link #(
|
|
.CMOS_LVDS_N (CMOS_LVDS_N),
|
|
.CLK_DIV_IS_FAST_CLK (FPGA_TECHNOLOGY >= 100)
|
|
) i_tx_2_link (
|
|
.dac_clk_div (dac_2_clk_div),
|
|
.dac_data_0 (dac_2_data_0),
|
|
.dac_data_1 (dac_2_data_1),
|
|
.dac_data_2 (dac_2_data_2),
|
|
.dac_data_3 (dac_2_data_3),
|
|
.dac_data_strobe (dac_2_data_strobe),
|
|
.dac_data_clk (dac_2_data_clk),
|
|
.dac_data_valid (dac_2_data_valid),
|
|
// DAC interface
|
|
.tx_clk (tx2_clk),
|
|
.tx_rst (tx2_rst),
|
|
.tx_data_valid (tx2_data_valid),
|
|
.tx_data_i (tx2_data_i),
|
|
.tx_data_q (tx2_data_q),
|
|
.tx_sdr_ddr_n (tx2_sdr_ddr_n),
|
|
.tx_single_lane (tx2_single_lane),
|
|
.tx_symb_op (tx2_symb_op),
|
|
.tx_symb_8_16b (tx2_symb_8_16b)
|
|
);
|
|
end else begin
|
|
assign tx2_clk = 1'b0;
|
|
assign tx2_dclk_out_n_NC = 1'b0;
|
|
assign tx2_dclk_out_p_dclk_out = 1'b0;
|
|
assign tx2_idata_out_n_idata0 = 1'b0;
|
|
assign tx2_idata_out_p_idata1 = 1'b0;
|
|
assign tx2_qdata_out_n_qdata2 = 1'b0;
|
|
assign tx2_qdata_out_p_qdata3 = 1'b0;
|
|
assign tx2_strobe_out_n_NC = 1'b0;
|
|
assign tx2_strobe_out_p_strobe_out = 1'b0;
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|