483 lines
19 KiB
Tcl
483 lines
19 KiB
Tcl
#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
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# by using this source code/core.
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#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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# This core is free software, you can use run, copy, study, change, ask
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# questions about and improve this core. Distribution of source, or resulting
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# binaries (including those inside an FPGA or ASIC) require you to release the
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# source of the entire project (excluding the system libraries provide by the
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# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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# License version 2 as published by the Free Software Foundation.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License version 2
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# along with this source code, and binary. If not, see
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# <http://www.gnu.org/licenses/>.
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
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# available under terms different than the General Public License. (e.g. they
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# do not require you to accompany any image (FPGA or ASIC) using the JESD204
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# core with any corresponding source code.) For these alternate terms you must
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# purchase a license from Analog Devices Technology Licensing Office. Users
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# interested in such a license should contact jesd204-licensing@analog.com for
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# more information. This commercial license is sub-licensable (if you purchase
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# chips from Analog Devices, incorporate them into your PCB level product, and
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# purchase a JESD204 license, end users of your product will also have a
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# license to use this core in a commercial setting without releasing their
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# source code).
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
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# or publication in which you use this JESD204 HDL core. (You are not required
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# to do so; it is up to your common sense to decide whether you want to comply
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# with this request or not.) For general publications, we suggest referencing :
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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proc adi_axi_jesd204_tx_create {ip_name num_lanes {num_links 1} {link_mode 1}} {
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if {$num_lanes < 1 || $num_lanes > 16} {
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return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-16)"
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}
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if {$num_links < 1 || $num_links > 8} {
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return -code 1 "ERROR: Invalid number of JESD204B links. (Supported range 1-8)"
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}
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startgroup
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set result [catch {
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create_bd_cell -type hier $ip_name
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ad_ip_instance axi_jesd204_tx "${ip_name}/tx_axi"
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ad_ip_instance jesd204_tx "${ip_name}/tx"
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ad_ip_parameter "${ip_name}/tx_axi" CONFIG.NUM_LANES $num_lanes
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ad_ip_parameter "${ip_name}/tx_axi" CONFIG.NUM_LINKS $num_links
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ad_ip_parameter "${ip_name}/tx_axi" CONFIG.LINK_MODE $link_mode
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ad_ip_parameter "${ip_name}/tx" CONFIG.NUM_LANES $num_lanes
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ad_ip_parameter "${ip_name}/tx" CONFIG.NUM_LINKS $num_links
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ad_ip_parameter "${ip_name}/tx" CONFIG.LINK_MODE $link_mode
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ad_connect "${ip_name}/tx_axi/core_reset" "${ip_name}/tx/reset"
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ad_connect "${ip_name}/tx_axi/device_reset" "${ip_name}/tx/device_reset"
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if {$link_mode == 1} {ad_connect "${ip_name}/tx_axi/tx_ctrl" "${ip_name}/tx/tx_ctrl"}
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ad_connect "${ip_name}/tx_axi/tx_cfg" "${ip_name}/tx/tx_cfg"
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ad_connect "${ip_name}/tx/tx_event" "${ip_name}/tx_axi/tx_event"
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ad_connect "${ip_name}/tx/tx_status" "${ip_name}/tx_axi/tx_status"
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if {$link_mode == 1} {ad_connect "${ip_name}/tx/tx_ilas_config" "${ip_name}/tx_axi/tx_ilas_config"}
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# Control interface
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create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk"
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create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn"
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi"
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create_bd_pin -dir O -type intr "${ip_name}/irq"
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ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/tx_axi/s_axi_aclk"
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ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/tx_axi/s_axi_aresetn"
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ad_connect "${ip_name}/s_axi" "${ip_name}/tx_axi/s_axi"
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ad_connect "${ip_name}/tx_axi/irq" "${ip_name}/irq"
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# JESD204 processing
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create_bd_pin -dir I -type clk "${ip_name}/link_clk"
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create_bd_pin -dir I -type clk "${ip_name}/device_clk"
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if {$link_mode == 1} {create_bd_pin -dir I -from [expr $num_links - 1] -to 0 "${ip_name}/sync"}
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create_bd_pin -dir I "${ip_name}/sysref"
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/tx_data"
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ad_connect "${ip_name}/link_clk" "${ip_name}/tx_axi/core_clk"
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ad_connect "${ip_name}/link_clk" "${ip_name}/tx/clk"
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ad_connect "${ip_name}/device_clk" "${ip_name}/tx_axi/device_clk"
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ad_connect "${ip_name}/device_clk" "${ip_name}/tx/device_clk"
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if {$link_mode == 1} {ad_connect "${ip_name}/sync" "${ip_name}/tx/sync"}
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ad_connect "${ip_name}/sysref" "${ip_name}/tx/sysref"
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ad_connect "${ip_name}/tx_data" "${ip_name}/tx/tx_data"
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for {set i 0} {$i < $num_lanes} {incr i} {
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create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 "${ip_name}/tx_phy${i}"
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ad_connect "${ip_name}/tx/tx_phy${i}" "${ip_name}/tx_phy${i}"
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}
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} resulttext resultoptions]
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dict unset resultoptions -level
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endgroup
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if {$result != 0} {
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undo -quiet
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}
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return -options $resultoptions $resulttext
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}
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proc adi_axi_jesd204_rx_create {ip_name num_lanes {num_links 1} {link_mode 1}} {
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if {$num_lanes < 1 || $num_lanes > 16} {
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return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-16)"
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}
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if {$num_links < 1 || $num_links > 8} {
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return -code 1 "ERROR: Invalid number of JESD204B links. (Supported range 1-8)"
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}
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startgroup
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set result [catch {
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create_bd_cell -type hier $ip_name
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ad_ip_instance axi_jesd204_rx "${ip_name}/rx_axi"
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ad_ip_instance jesd204_rx "${ip_name}/rx"
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ad_ip_parameter "${ip_name}/rx_axi" CONFIG.NUM_LANES $num_lanes
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ad_ip_parameter "${ip_name}/rx_axi" CONFIG.NUM_LINKS $num_links
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ad_ip_parameter "${ip_name}/rx_axi" CONFIG.LINK_MODE $link_mode
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ad_ip_parameter "${ip_name}/rx" CONFIG.NUM_LANES $num_lanes
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ad_ip_parameter "${ip_name}/rx" CONFIG.NUM_LINKS $num_links
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ad_ip_parameter "${ip_name}/rx" CONFIG.LINK_MODE $link_mode
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ad_connect "${ip_name}/rx_axi/core_reset" "${ip_name}/rx/reset"
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ad_connect "${ip_name}/rx_axi/device_reset" "${ip_name}/rx/device_reset"
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ad_connect "${ip_name}/rx_axi/rx_cfg" "${ip_name}/rx/rx_cfg"
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ad_connect "${ip_name}/rx/rx_event" "${ip_name}/rx_axi/rx_event"
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ad_connect "${ip_name}/rx/rx_status" "${ip_name}/rx_axi/rx_status"
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if {$link_mode == 1} {ad_connect "${ip_name}/rx/rx_ilas_config" "${ip_name}/rx_axi/rx_ilas_config"}
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# Control interface
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create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk"
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create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn"
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi"
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create_bd_pin -dir O -type intr "${ip_name}/irq"
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ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/rx_axi/s_axi_aclk"
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ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/rx_axi/s_axi_aresetn"
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ad_connect "${ip_name}/s_axi" "${ip_name}/rx_axi/s_axi"
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ad_connect "${ip_name}/rx_axi/irq" "${ip_name}/irq"
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# JESD204 processing
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create_bd_pin -dir I -type clk "${ip_name}/link_clk"
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create_bd_pin -dir I -type clk "${ip_name}/device_clk"
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if {$link_mode == 1} {create_bd_pin -dir O -from [expr $num_links - 1] -to 0 "${ip_name}/sync"}
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create_bd_pin -dir I "${ip_name}/sysref"
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if {$link_mode == 1} {create_bd_pin -dir O "${ip_name}/phy_en_char_align"}
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# create_bd_pin -dir I "${ip_name}/phy_ready"
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create_bd_pin -dir O -from 3 -to 0 "${ip_name}/rx_eof"
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create_bd_pin -dir O -from 3 -to 0 "${ip_name}/rx_sof"
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# create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/rx_data"
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create_bd_pin -dir O "${ip_name}/rx_data_tvalid"
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create_bd_pin -dir O -from [expr $num_lanes * 32 - 1] -to 0 "${ip_name}/rx_data_tdata"
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ad_connect "${ip_name}/link_clk" "${ip_name}/rx_axi/core_clk"
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ad_connect "${ip_name}/link_clk" "${ip_name}/rx/clk"
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ad_connect "${ip_name}/device_clk" "${ip_name}/rx_axi/device_clk"
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ad_connect "${ip_name}/device_clk" "${ip_name}/rx/device_clk"
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if {$link_mode == 1} {ad_connect "${ip_name}/rx/sync" "${ip_name}/sync"}
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ad_connect "${ip_name}/sysref" "${ip_name}/rx/sysref"
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# ad_connect "${ip_name}/phy_ready" "${ip_name}/rx/phy_ready"
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if {$link_mode == 1} {ad_connect "${ip_name}/rx/phy_en_char_align" "${ip_name}/phy_en_char_align"}
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ad_connect "${ip_name}/rx/rx_data" "${ip_name}/rx_data_tdata"
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ad_connect "${ip_name}/rx/rx_valid" "${ip_name}/rx_data_tvalid"
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ad_connect "${ip_name}/rx/rx_eof" "${ip_name}/rx_eof"
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ad_connect "${ip_name}/rx/rx_sof" "${ip_name}/rx_sof"
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for {set i 0} {$i < $num_lanes} {incr i} {
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 "${ip_name}/rx_phy${i}"
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ad_connect "${ip_name}/rx/rx_phy${i}" "${ip_name}/rx_phy${i}"
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}
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} resulttext resultoptions]
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dict unset resultoptions -level
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endgroup
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if {$result != 0} {
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undo -quiet
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}
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return -options $resultoptions $resulttext
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}
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# L M S N & NP
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proc adi_tpl_jesd204_tx_create {ip_name num_of_lanes num_of_converters samples_per_frame sample_width {link_layer_bytes_per_beat 4} {dma_sample_width 16}} {
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if {$num_of_lanes < 1 || $num_of_lanes > 16} {
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return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-16)"
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}
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# F = (M * N * S) / (L * 8)
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set bytes_per_frame [expr ($num_of_converters * $sample_width * $samples_per_frame) / ($num_of_lanes * 8)];
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# one beat per lane must accommodate at least one frame
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set tpl_bytes_per_beat [expr max($bytes_per_frame, $link_layer_bytes_per_beat)]
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# datapath width = L * 8 * TPL_BYTES_PER_BEAT / (M * N)
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set samples_per_channel [expr ($num_of_lanes * 8 * $tpl_bytes_per_beat) / ($num_of_converters * $sample_width)];
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startgroup
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set result [catch {
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create_bd_cell -type hier $ip_name
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# Control interface
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create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk"
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create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn"
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi"
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# Interface to link layer
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create_bd_pin -dir I -type clk "${ip_name}/link_clk"
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/link"
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# Interface to application layer
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create_bd_pin -dir I "${ip_name}/dac_dunf"
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for {set i 0} {$i < $num_of_converters} {incr i} {
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create_bd_pin -dir O "${ip_name}/dac_enable_${i}"
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create_bd_pin -dir O "${ip_name}/dac_valid_${i}"
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create_bd_pin -dir I "${ip_name}/dac_data_${i}"
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}
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# Generic TPL core
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ad_ip_instance ad_ip_jesd204_tpl_dac "${ip_name}/dac_tpl_core" [list \
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NUM_LANES $num_of_lanes \
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NUM_CHANNELS $num_of_converters \
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SAMPLES_PER_FRAME $samples_per_frame \
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CONVERTER_RESOLUTION $sample_width \
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BITS_PER_SAMPLE $sample_width \
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OCTETS_PER_BEAT $tpl_bytes_per_beat \
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DMA_BITS_PER_SAMPLE $dma_sample_width
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]
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if {$num_of_converters > 1} {
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# Concatenation and slicer cores
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# xconcat limited to 32 input ports
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for {set i 0} {$i < $num_of_converters} {incr i 32} {
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ad_ip_instance xlconcat "${ip_name}/data_concat[expr $i/32]" [list \
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NUM_PORTS [expr min(32,$num_of_converters-$i)] \
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]
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}
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# main concat
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if {$num_of_converters > 32} {
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ad_ip_instance xlconcat "${ip_name}/data_concat" [list \
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NUM_PORTS [expr int(ceil(double($num_of_converters)/32))] \
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]
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}
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for {set i 0} {$i < $num_of_converters} {incr i} {
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ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \
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DIN_WIDTH $num_of_converters \
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DIN_FROM $i \
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DIN_TO $i \
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]
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ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \
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DIN_WIDTH $num_of_converters \
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DIN_FROM $i \
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DIN_TO $i \
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]
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}
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}
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# Create connections
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# TPL configuration interface
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ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/dac_tpl_core/s_axi_aclk"
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ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/dac_tpl_core/s_axi_aresetn"
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ad_connect "${ip_name}/s_axi" "${ip_name}/dac_tpl_core/s_axi"
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# TPL - link layer
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ad_connect ${ip_name}/dac_tpl_core/link_clk ${ip_name}/link_clk
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ad_connect ${ip_name}/dac_tpl_core/link ${ip_name}/link
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# TPL - app layer
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if {$num_of_converters > 1} {
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for {set i 0} {$i < $num_of_converters} {incr i} {
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ad_connect ${ip_name}/dac_tpl_core/enable ${ip_name}/enable_slice_$i/Din
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ad_connect ${ip_name}/dac_tpl_core/dac_valid ${ip_name}/valid_slice_$i/Din
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ad_connect ${ip_name}/enable_slice_$i/Dout ${ip_name}/dac_enable_$i
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ad_connect ${ip_name}/valid_slice_$i/Dout ${ip_name}/dac_valid_$i
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ad_connect ${ip_name}/dac_data_$i ${ip_name}/data_concat[expr $i/32]/In[expr $i%32]
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}
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if {$num_of_converters > 32} {
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# wire all concatenators together
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for {set i 0} {$i < $num_of_converters} {incr i 32} {
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ad_connect ${ip_name}/data_concat[expr $i/32]/dout ${ip_name}/data_concat/In[expr $i/32]
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}
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ad_connect ${ip_name}/data_concat/dout ${ip_name}/dac_tpl_core/dac_ddata
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} else {
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ad_connect ${ip_name}/data_concat0/dout ${ip_name}/dac_tpl_core/dac_ddata
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}
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} else {
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ad_connect ${ip_name}/dac_data_0 ${ip_name}/dac_tpl_core/dac_ddata
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ad_connect ${ip_name}/dac_tpl_core/enable ${ip_name}/dac_enable_0
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ad_connect ${ip_name}/dac_tpl_core/dac_valid ${ip_name}/dac_valid_0
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}
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ad_connect ${ip_name}/dac_dunf ${ip_name}/dac_tpl_core/dac_dunf
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} resulttext resultoptions]
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dict unset resultoptions -level
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endgroup
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if {$result != 0} {
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undo -quiet
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}
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return -options $resultoptions $resulttext
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}
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# L M S N & NP
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proc adi_tpl_jesd204_rx_create {ip_name num_of_lanes num_of_converters samples_per_frame sample_width {link_layer_bytes_per_beat 4} {dma_sample_width 16}} {
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if {$num_of_lanes < 1 || $num_of_lanes > 16} {
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return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-16)"
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}
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# F = (M * N * S) / (L * 8)
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set bytes_per_frame [expr ($num_of_converters * $sample_width * $samples_per_frame) / ($num_of_lanes * 8)];
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# one beat per lane must accommodate at least one frame
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set tpl_bytes_per_beat [expr max($bytes_per_frame, $link_layer_bytes_per_beat)]
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# datapath width = L * 8 * TPL_BYTES_PER_BEAT / (M * N)
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set samples_per_channel [expr ($num_of_lanes * 8 * $tpl_bytes_per_beat) / ($num_of_converters * $sample_width)];
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startgroup
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set result [catch {
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create_bd_cell -type hier $ip_name
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# Control interface
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create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk"
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create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn"
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi"
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# Interface to link layer
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create_bd_pin -dir I -type clk "${ip_name}/link_clk"
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#create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/link"
|
|
create_bd_pin -dir I "${ip_name}/link_sof"
|
|
create_bd_pin -dir I "${ip_name}/link_valid"
|
|
create_bd_pin -dir I "${ip_name}/link_data"
|
|
|
|
# Interface to application layer
|
|
create_bd_pin -dir I "${ip_name}/adc_dovf"
|
|
for {set i 0} {$i < $num_of_converters} {incr i} {
|
|
create_bd_pin -dir O "${ip_name}/adc_enable_${i}"
|
|
create_bd_pin -dir O "${ip_name}/adc_valid_${i}"
|
|
create_bd_pin -dir O "${ip_name}/adc_data_${i}"
|
|
}
|
|
|
|
# Generic TPL core
|
|
ad_ip_instance ad_ip_jesd204_tpl_adc "${ip_name}/adc_tpl_core" [list \
|
|
NUM_LANES $num_of_lanes \
|
|
NUM_CHANNELS $num_of_converters \
|
|
SAMPLES_PER_FRAME $samples_per_frame \
|
|
CONVERTER_RESOLUTION $sample_width \
|
|
BITS_PER_SAMPLE $sample_width \
|
|
OCTETS_PER_BEAT $tpl_bytes_per_beat \
|
|
DMA_BITS_PER_SAMPLE $dma_sample_width
|
|
]
|
|
|
|
if {$num_of_converters > 1} {
|
|
# Slicer cores
|
|
for {set i 0} {$i < $num_of_converters} {incr i} {
|
|
ad_ip_instance xlslice ${ip_name}/data_slice_$i [list \
|
|
DIN_WIDTH [expr $dma_sample_width*$samples_per_channel*$num_of_converters] \
|
|
DIN_FROM [expr $dma_sample_width*$samples_per_channel*($i+1)-1] \
|
|
DIN_TO [expr $dma_sample_width*$samples_per_channel*$i] \
|
|
]
|
|
|
|
ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \
|
|
DIN_WIDTH $num_of_converters \
|
|
DIN_FROM $i \
|
|
DIN_TO $i \
|
|
]
|
|
ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \
|
|
DIN_WIDTH $num_of_converters \
|
|
DIN_FROM $i \
|
|
DIN_TO $i \
|
|
]
|
|
}
|
|
}
|
|
|
|
# Create connections
|
|
# TPL configuration interface
|
|
ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/adc_tpl_core/s_axi_aclk"
|
|
ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/adc_tpl_core/s_axi_aresetn"
|
|
ad_connect "${ip_name}/s_axi" "${ip_name}/adc_tpl_core/s_axi"
|
|
|
|
# TPL - link layer
|
|
ad_connect ${ip_name}/adc_tpl_core/link_clk ${ip_name}/link_clk
|
|
#ad_connect ${ip_name}/adc_tpl_core/link ${ip_name}/link
|
|
ad_connect ${ip_name}/adc_tpl_core/link_sof ${ip_name}/link_sof
|
|
ad_connect ${ip_name}/adc_tpl_core/link_data ${ip_name}/link_data
|
|
ad_connect ${ip_name}/adc_tpl_core/link_valid ${ip_name}/link_valid
|
|
|
|
# TPL - app layer
|
|
if {$num_of_converters > 1} {
|
|
for {set i 0} {$i < $num_of_converters} {incr i} {
|
|
ad_connect ${ip_name}/adc_tpl_core/adc_data ${ip_name}/data_slice_$i/Din
|
|
ad_connect ${ip_name}/adc_tpl_core/enable ${ip_name}/enable_slice_$i/Din
|
|
ad_connect ${ip_name}/adc_tpl_core/adc_valid ${ip_name}/valid_slice_$i/Din
|
|
|
|
ad_connect ${ip_name}/data_slice_$i/Dout ${ip_name}/adc_data_$i
|
|
ad_connect ${ip_name}/enable_slice_$i/Dout ${ip_name}/adc_enable_$i
|
|
ad_connect ${ip_name}/valid_slice_$i/Dout ${ip_name}/adc_valid_$i
|
|
|
|
}
|
|
} else {
|
|
ad_connect ${ip_name}/adc_tpl_core/adc_data ${ip_name}/adc_data_0
|
|
ad_connect ${ip_name}/adc_tpl_core/enable ${ip_name}/adc_enable_0
|
|
ad_connect ${ip_name}/adc_tpl_core/adc_valid ${ip_name}/adc_valid_0
|
|
}
|
|
ad_connect ${ip_name}/adc_dovf ${ip_name}/adc_tpl_core/adc_dovf
|
|
|
|
} resulttext resultoptions]
|
|
|
|
dict unset resultoptions -level
|
|
|
|
endgroup
|
|
|
|
if {$result != 0} {
|
|
undo -quiet
|
|
}
|
|
|
|
return -options $resultoptions $resulttext
|
|
}
|
|
|
|
# Calculate Link Layer interface width towards Transport Layer
|
|
# TPL width must be set to an integer multiple of F
|
|
proc adi_jesd204_calc_tpl_width {link_datapath_width jesd_l jesd_m jesd_s jesd_np} {
|
|
|
|
set jesd_f [expr ($jesd_m*$jesd_s*$jesd_np)/(8*$jesd_l)]
|
|
|
|
# For F=3,6,12 get first pow 2 multiple of F greater than link_datapath_width
|
|
if {$jesd_f % 3 == 0} {
|
|
set np12_datapath_width $jesd_f
|
|
while {$np12_datapath_width < $link_datapath_width} {
|
|
set np12_datapath_width [expr 2*$np12_datapath_width]
|
|
}
|
|
return $np12_datapath_width
|
|
} else {
|
|
return [expr max($jesd_f,$link_datapath_width)]
|
|
}
|
|
|
|
}
|
|
|
|
|