333 lines
13 KiB
Verilog
Executable File
333 lines
13 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_adc_pack (
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clk,
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chan_data_0,
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chan_data_1,
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chan_data_2,
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chan_data_3,
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chan_enable_0,
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chan_enable_1,
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chan_enable_2,
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chan_enable_3,
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chan_valid_0,
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chan_valid_1,
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chan_valid_2,
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chan_valid_3,
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ddata,
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dvalid,
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dsync
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);
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// common clock
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input clk;
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input [15:0] chan_data_0;
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input [15:0] chan_data_1;
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input [15:0] chan_data_2;
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input [15:0] chan_data_3;
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input chan_enable_0;
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input chan_enable_1;
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input chan_enable_2;
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input chan_enable_3;
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input chan_valid_0;
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input chan_valid_1;
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input chan_valid_2;
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input chan_valid_3;
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output [63:0] ddata;
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output dvalid;
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output dsync;
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reg [47:0] adc_data_3_1110 = 'd0;
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reg [47:0] adc_data_3_1101 = 'd0;
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reg [47:0] adc_data_3_1011 = 'd0;
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reg [47:0] adc_data_3_0111 = 'd0;
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reg adc_iqcor_valid = 'd0;
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reg adc_iqcor_valid_3 = 'd0;
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reg adc_iqcor_sync = 'd0;
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reg adc_iqcor_sync_3 = 'd0;
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reg [63:0] adc_data = 'd0;
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reg [63:0] adc_data_1110 = 'd0;
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reg [63:0] adc_data_1101 = 'd0;
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reg [63:0] adc_data_1011 = 'd0;
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reg [63:0] adc_data_0111 = 'd0;
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reg [ 1:0] adc_data_cnt = 'd0;
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wire valid;
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assign dsync = adc_iqcor_sync;
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assign dvalid = adc_iqcor_valid;
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assign ddata = adc_data;
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assign valid = chan_valid_0 & chan_valid_1 & chan_valid_2 & chan_valid_3;
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always @(posedge clk) begin
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if (valid == 1'b1) begin
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adc_iqcor_valid_3 <= adc_data_cnt[0] | adc_data_cnt[1];
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adc_iqcor_sync_3 <= adc_data_cnt[0] & ~adc_data_cnt[1];
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adc_data_3_1110[47:32] <= chan_data_3;
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adc_data_3_1110[31:16] <= chan_data_2;
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adc_data_3_1110[15: 0] <= chan_data_1;
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adc_data_3_1101[47:32] <= chan_data_3;
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adc_data_3_1101[31:16] <= chan_data_2;
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adc_data_3_1101[15: 0] <= chan_data_0;
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adc_data_3_1011[47:32] <= chan_data_3;
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adc_data_3_1011[31:16] <= chan_data_1;
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adc_data_3_1011[15: 0] <= chan_data_0;
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adc_data_3_0111[47:32] <= chan_data_2;
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adc_data_3_0111[31:16] <= chan_data_1;
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adc_data_3_0111[15: 0] <= chan_data_0;
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case (adc_data_cnt)
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2'b11: begin
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adc_data_1110[63:48] <= chan_data_3;
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adc_data_1110[47:32] <= chan_data_2;
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adc_data_1110[31:16] <= chan_data_1;
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adc_data_1110[15: 0] <= adc_data_3_1110[47:32];
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adc_data_1101[63:48] <= chan_data_3;
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adc_data_1101[47:32] <= chan_data_2;
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adc_data_1101[31:16] <= chan_data_0;
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adc_data_1101[15: 0] <= adc_data_3_1101[47:32];
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adc_data_1011[63:48] <= chan_data_3;
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adc_data_1011[47:32] <= chan_data_1;
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adc_data_1011[31:16] <= chan_data_0;
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adc_data_1011[15: 0] <= adc_data_3_1011[47:32];
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adc_data_0111[63:48] <= chan_data_2;
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adc_data_0111[47:32] <= chan_data_1;
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adc_data_0111[31:16] <= chan_data_0;
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adc_data_0111[15: 0] <= adc_data_3_0111[47:32];
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end
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2'b10: begin
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adc_data_1110[63:48] <= chan_data_2;
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adc_data_1110[47:32] <= chan_data_1;
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adc_data_1110[31:16] <= adc_data_3_1110[47:32];
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adc_data_1110[15: 0] <= adc_data_3_1110[31:16];
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adc_data_1101[63:48] <= chan_data_2;
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adc_data_1101[47:32] <= chan_data_0;
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adc_data_1101[31:16] <= adc_data_3_1101[47:32];
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adc_data_1101[15: 0] <= adc_data_3_1101[31:16];
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adc_data_1011[63:48] <= chan_data_1;
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adc_data_1011[47:32] <= chan_data_0;
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adc_data_1011[31:16] <= adc_data_3_1011[47:32];
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adc_data_1011[15: 0] <= adc_data_3_1011[31:16];
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adc_data_0111[63:48] <= chan_data_1;
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adc_data_0111[47:32] <= chan_data_0;
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adc_data_0111[31:16] <= adc_data_3_0111[47:32];
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adc_data_0111[15: 0] <= adc_data_3_0111[31:16];
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end
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2'b01: begin
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adc_data_1110[63:48] <= chan_data_1;
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adc_data_1110[47:32] <= adc_data_3_1110[47:32];
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adc_data_1110[31:16] <= adc_data_3_1110[31:16];
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adc_data_1110[15: 0] <= adc_data_3_1110[15: 0];
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adc_data_1101[63:48] <= chan_data_0;
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adc_data_1101[47:32] <= adc_data_3_1101[47:32];
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adc_data_1101[31:16] <= adc_data_3_1101[31:16];
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adc_data_1101[15: 0] <= adc_data_3_1101[15: 0];
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adc_data_1011[63:48] <= chan_data_0;
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adc_data_1011[47:32] <= adc_data_3_1011[47:32];
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adc_data_1011[31:16] <= adc_data_3_1011[31:16];
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adc_data_1011[15: 0] <= adc_data_3_1011[15: 0];
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adc_data_0111[63:48] <= chan_data_0;
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adc_data_0111[47:32] <= adc_data_3_0111[47:32];
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adc_data_0111[31:16] <= adc_data_3_0111[31:16];
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adc_data_0111[15: 0] <= adc_data_3_0111[15: 0];
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end
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default:begin
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adc_data_1110[63:48] <= 16'hdead;
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adc_data_1110[47:32] <= 16'hdead;
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adc_data_1110[31:16] <= 16'hdead;
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adc_data_1110[15: 0] <= 16'hdead;
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adc_data_1101[63:48] <= 16'hdead;
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adc_data_1101[47:32] <= 16'hdead;
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adc_data_1101[31:16] <= 16'hdead;
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adc_data_1101[15: 0] <= 16'hdead;
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adc_data_1011[63:48] <= 16'hdead;
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adc_data_1011[47:32] <= 16'hdead;
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adc_data_1011[31:16] <= 16'hdead;
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adc_data_1011[15: 0] <= 16'hdead;
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adc_data_0111[63:48] <= 16'hdead;
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adc_data_0111[47:32] <= 16'hdead;
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adc_data_0111[31:16] <= 16'hdead;
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adc_data_0111[15: 0] <= 16'hdead;
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end
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endcase
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end
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end
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always @(posedge clk) begin
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if (valid == 1'b1) begin
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case ({chan_enable_3, chan_enable_2, chan_enable_1, chan_enable_0})
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4'b1111: begin
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adc_iqcor_valid <= 1'b1;
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adc_iqcor_sync <= 1'b1;
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adc_data[63:48] <= chan_data_3;
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adc_data[47:32] <= chan_data_2;
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adc_data[31:16] <= chan_data_1;
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adc_data[15: 0] <= chan_data_0;
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end
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4'b1110: begin
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adc_iqcor_sync <= adc_iqcor_sync_3;
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adc_iqcor_valid <= adc_iqcor_valid_3;
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adc_data <= adc_data_1110;
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end
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4'b1101: begin
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adc_iqcor_sync <= adc_iqcor_sync_3;
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adc_iqcor_valid <= adc_iqcor_valid_3;
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adc_data <= adc_data_1101;
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end
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4'b1100: begin
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adc_iqcor_sync <= 1'b1;
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adc_iqcor_valid <= adc_data_cnt[0];
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adc_data[63:48] <= chan_data_3;
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adc_data[47:32] <= chan_data_2;
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adc_data[31:16] <= adc_data[63:48];
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adc_data[15: 0] <= adc_data[47:32];
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end
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4'b1011: begin
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adc_iqcor_sync <= adc_iqcor_sync_3;
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adc_iqcor_valid <= adc_iqcor_valid_3;
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adc_data <= adc_data_1011;
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end
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4'b1010: begin
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adc_iqcor_sync <= 1'b1;
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adc_iqcor_valid <= adc_data_cnt[0];
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adc_data[63:48] <= chan_data_3;
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adc_data[47:32] <= chan_data_1;
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adc_data[31:16] <= adc_data[63:48];
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adc_data[15: 0] <= adc_data[47:32];
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end
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4'b1001: begin
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adc_iqcor_sync <= 1'b1;
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adc_iqcor_valid <= adc_data_cnt[0];
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adc_data[63:48] <= chan_data_3;
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adc_data[47:32] <= chan_data_0;
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adc_data[31:16] <= adc_data[63:48];
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adc_data[15: 0] <= adc_data[47:32];
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end
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4'b1000: begin
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adc_iqcor_sync <= 1'b1;
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adc_iqcor_valid <= adc_data_cnt[1] & adc_data_cnt[0];
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adc_data[63:48] <= chan_data_3;
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adc_data[47:32] <= adc_data[63:48];
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adc_data[31:16] <= adc_data[47:32];
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adc_data[15: 0] <= adc_data[31:16];
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end
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4'b0111: begin
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adc_iqcor_sync <= adc_iqcor_sync_3;
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adc_iqcor_valid <= adc_iqcor_valid_3;
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adc_data <= adc_data_0111;
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end
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4'b0110: begin
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adc_iqcor_sync <= 1'b1;
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adc_iqcor_valid <= adc_data_cnt[0];
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adc_data[63:48] <= chan_data_2;
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adc_data[47:32] <= chan_data_1;
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adc_data[31:16] <= adc_data[63:48];
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adc_data[15: 0] <= adc_data[47:32];
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end
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4'b0101: begin
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adc_iqcor_sync <= 1'b1;
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adc_iqcor_valid <= adc_data_cnt[0];
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adc_data[63:48] <= chan_data_2;
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adc_data[47:32] <= chan_data_0;
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adc_data[31:16] <= adc_data[63:48];
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adc_data[15: 0] <= adc_data[47:32];
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end
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4'b0100: begin
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adc_iqcor_sync <= 1'b1;
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adc_iqcor_valid <= adc_data_cnt[1] & adc_data_cnt[0];
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adc_data[63:48] <= chan_data_2;
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adc_data[47:32] <= adc_data[63:48];
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adc_data[31:16] <= adc_data[47:32];
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adc_data[15: 0] <= adc_data[31:16];
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end
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4'b0011: begin
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adc_iqcor_sync <= 1'b1;
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adc_iqcor_valid <= adc_data_cnt[0];
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adc_data[63:48] <= chan_data_1;
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adc_data[47:32] <= chan_data_0;
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adc_data[31:16] <= adc_data[63:48];
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adc_data[15: 0] <= adc_data[47:32];
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end
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4'b0010: begin
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adc_iqcor_sync <= 1'b1;
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adc_iqcor_valid <= adc_data_cnt[1] & adc_data_cnt[0];
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adc_data[63:48] <= chan_data_1;
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adc_data[47:32] <= adc_data[63:48];
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adc_data[31:16] <= adc_data[47:32];
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adc_data[15: 0] <= adc_data[31:16];
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end
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4'b0001: begin
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adc_iqcor_sync <= 1'b1;
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adc_iqcor_valid <= adc_data_cnt[1] & adc_data_cnt[0];
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adc_data[63:48] <= chan_data_0;
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adc_data[47:32] <= adc_data[63:48];
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adc_data[31:16] <= adc_data[47:32];
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adc_data[15: 0] <= adc_data[31:16];
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end
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default: begin
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adc_iqcor_valid <= 1'b1;
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adc_data[63:48] <= 16'hdead;
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adc_data[47:32] <= 16'hdead;
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adc_data[31:16] <= 16'hdead;
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adc_data[15: 0] <= 16'hdead;
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end
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endcase
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adc_data_cnt <= adc_data_cnt + 1'b1;
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end else begin
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adc_iqcor_valid <= 1'b0;
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adc_data <= adc_data;
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adc_data_cnt <= adc_data_cnt;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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