146 lines
4.1 KiB
Verilog
146 lines
4.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_upack_tb;
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parameter VCD_FILE = "ad_upack_tb.vcd";
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parameter I_W = 6; // Width of input channel
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parameter O_W = 4; // Width of output channel
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parameter UNIT_W = 8;
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parameter VECT_W = 1024*8; // Multiple of 8
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`include "tb_base.v"
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reg [I_W*UNIT_W-1 : 0] idata;
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wire [O_W*UNIT_W-1 : 0] odata;
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reg ivalid = 'b0;
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reg [VECT_W-1:0] input_vector;
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reg [VECT_W-1:0] output_vector;
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integer i=0;
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integer j=0;
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ad_upack #(
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.I_W(I_W),
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.O_W(O_W),
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.UNIT_W(UNIT_W)
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) DUT (
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.clk(clk),
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.reset(reset),
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.idata(idata),
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.iready(iready),
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.ivalid(ivalid),
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.odata(odata),
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.ovalid(ovalid));
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task test(input no_random);
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begin
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@(posedge clk);
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i = 0;
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j = 0;
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while (i < VECT_W/(I_W*UNIT_W)) begin
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@(posedge clk);
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if (iready & (($urandom % 2 == 0) | no_random)) begin
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idata <= input_vector[i*(I_W*UNIT_W) +: (I_W*UNIT_W)];
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ivalid <= 1'b1;
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i = i + 1;
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end else begin
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idata <= 'bx;
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ivalid <= 1'b0;
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end
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end
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@(posedge clk);
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idata <= 'bx;
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ivalid <= 1'b0;
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// Check output vector
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repeat (20) @(posedge clk);
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for (i=0; i<(((VECT_W/(I_W*UNIT_W))*(I_W*UNIT_W))/(O_W*UNIT_W))*(O_W*UNIT_W)/8; i=i+1) begin
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if (input_vector[i*8+:8] !== output_vector[i*8+:8]) begin
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failed <= 1'b1;
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$display("i=%d Expected=%x Found=%x",i,input_vector[i*8+:8],output_vector[i*8+:8]);
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end
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end
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end
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endtask
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initial begin
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@(negedge reset);
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// Test with incremental data
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for (i=0; i<VECT_W/8; i=i+1) begin
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input_vector[i*8+:8] = i[7:0];
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output_vector[i*8+:8] = 'bx;
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end
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test(1);
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do_trigger_reset();
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@(negedge reset);
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// Test with incremental data random timing
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for (i=0; i<VECT_W/8; i=i+1) begin
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input_vector[i*8+:8] = i[7:0];
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output_vector[i*8+:8] = 'bx;
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end
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test(0);
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do_trigger_reset();
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@(negedge reset);
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// Test with randomized data random timing
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for (i=0; i<VECT_W/8; i=i+1) begin
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input_vector[i*8+:8] = $urandom;
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end
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test(0);
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end
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always @(posedge clk) begin
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if (ovalid) begin
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if (j < VECT_W/(O_W*UNIT_W)) begin
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output_vector[j*(O_W*UNIT_W) +: (O_W*UNIT_W)] = odata;
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j = j + 1;
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end
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end
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end
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endmodule
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