247 lines
6.7 KiB
Verilog
247 lines
6.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// serial data output interface: serdes(x8) or oddr(x2) output module
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`timescale 1ps/1ps
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module ad_serdes_out (
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// reset and clocks
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rst,
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clk,
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div_clk,
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// data interface
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data_s0,
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data_s1,
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data_s2,
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data_s3,
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data_s4,
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data_s5,
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data_s6,
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data_s7,
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data_out_p,
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data_out_n);
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// parameters
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parameter DEVICE_TYPE = 0;
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parameter SERDES = 1;
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parameter DATA_WIDTH = 16;
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localparam DEVICE_6SERIES = 1;
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localparam DEVICE_7SERIES = 0;
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localparam DW = DATA_WIDTH - 1;
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// reset and clocks
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input rst;
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input clk;
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input div_clk;
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// data interface
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input [DW:0] data_s0;
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input [DW:0] data_s1;
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input [DW:0] data_s2;
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input [DW:0] data_s3;
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input [DW:0] data_s4;
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input [DW:0] data_s5;
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input [DW:0] data_s6;
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input [DW:0] data_s7;
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output [DW:0] data_out_p;
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output [DW:0] data_out_n;
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// internal signals
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wire [DW:0] data_out_s;
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wire [DW:0] serdes_shift1_s;
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wire [DW:0] serdes_shift2_s;
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// instantiations
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genvar l_inst;
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generate
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for (l_inst = 0; l_inst <= DW; l_inst = l_inst + 1) begin: g_data
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if (SERDES == 0) begin
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ODDR #(
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.DDR_CLK_EDGE ("SAME_EDGE"),
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.INIT (1'b0),
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.SRTYPE ("ASYNC"))
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i_oddr (
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.S (1'b0),
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.CE (1'b1),
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.R (rst),
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.C (clk),
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.D1 (data_s0[l_inst]),
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.D2 (data_s1[l_inst]),
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.Q (data_out_s[l_inst]));
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end
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if ((SERDES == 1) && (DEVICE_TYPE == DEVICE_7SERIES)) begin
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OSERDESE2 #(
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.DATA_RATE_OQ ("DDR"),
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.DATA_RATE_TQ ("SDR"),
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.DATA_WIDTH (8),
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.TRISTATE_WIDTH (1),
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.SERDES_MODE ("MASTER"))
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i_serdes (
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.D1 (data_s0[l_inst]),
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.D2 (data_s1[l_inst]),
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.D3 (data_s2[l_inst]),
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.D4 (data_s3[l_inst]),
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.D5 (data_s4[l_inst]),
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.D6 (data_s5[l_inst]),
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.D7 (data_s6[l_inst]),
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.D8 (data_s7[l_inst]),
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.T1 (1'b0),
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.T2 (1'b0),
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.T3 (1'b0),
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.T4 (1'b0),
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.SHIFTIN1 (1'b0),
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.SHIFTIN2 (1'b0),
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.SHIFTOUT1 (),
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.SHIFTOUT2 (),
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.OCE (1'b1),
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.CLK (clk),
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.CLKDIV (div_clk),
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.OQ (data_out_s[l_inst]),
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.TQ (),
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.OFB (),
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.TFB (),
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.TBYTEIN (1'b0),
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.TBYTEOUT (),
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.TCE (1'b0),
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.RST (rst));
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end
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if ((SERDES == 1) && (DEVICE_TYPE == DEVICE_6SERIES)) begin
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OSERDESE1 #(
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.DATA_RATE_OQ ("DDR"),
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.DATA_RATE_TQ ("SDR"),
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.DATA_WIDTH (8),
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.INTERFACE_TYPE ("DEFAULT"),
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.TRISTATE_WIDTH (1),
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.SERDES_MODE ("MASTER"))
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i_serdes_m (
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.D1 (data_s0[l_inst]),
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.D2 (data_s1[l_inst]),
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.D3 (data_s2[l_inst]),
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.D4 (data_s3[l_inst]),
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.D5 (data_s4[l_inst]),
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.D6 (data_s5[l_inst]),
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.T1 (1'b0),
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.T2 (1'b0),
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.T3 (1'b0),
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.T4 (1'b0),
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.SHIFTIN1 (serdes_shift1_s[l_inst]),
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.SHIFTIN2 (serdes_shift2_s[l_inst]),
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.SHIFTOUT1 (),
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.SHIFTOUT2 (),
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.OCE (1'b1),
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.CLK (clk),
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.CLKDIV (div_clk),
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.CLKPERF (1'b0),
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.CLKPERFDELAY (1'b0),
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.WC (1'b0),
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.ODV (1'b0),
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.OQ (data_out_s[l_inst]),
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.TQ (),
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.OCBEXTEND (),
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.OFB (),
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.TFB (),
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.TCE (1'b0),
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.RST (rst));
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OSERDESE1 #(
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.DATA_RATE_OQ ("DDR"),
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.DATA_RATE_TQ ("SDR"),
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.DATA_WIDTH (8),
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.INTERFACE_TYPE ("DEFAULT"),
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.TRISTATE_WIDTH (1),
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.SERDES_MODE ("SLAVE"))
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i_serdes_s (
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.D1 (1'b0),
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.D2 (1'b0),
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.D3 (data_s6[l_inst]),
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.D4 (data_s7[l_inst]),
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.D5 (1'b0),
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.D6 (1'b0),
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.T1 (1'b0),
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.T2 (1'b0),
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.T3 (1'b0),
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.T4 (1'b0),
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.SHIFTIN1 (1'b0),
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.SHIFTIN2 (1'b0),
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.SHIFTOUT1 (serdes_shift1_s[l_inst]),
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.SHIFTOUT2 (serdes_shift2_s[l_inst]),
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.OCE (1'b1),
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.CLK (clk),
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.CLKDIV (div_clk),
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.CLKPERF (1'b0),
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.CLKPERFDELAY (1'b0),
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.WC (1'b0),
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.ODV (1'b0),
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.OQ (),
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.TQ (),
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.OCBEXTEND (),
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.OFB (),
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.TFB (),
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.TCE (1'b0),
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.RST (rst));
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end
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OBUFDS i_obuf (
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.I (data_out_s[l_inst]),
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.O (data_out_p[l_inst]),
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.OB (data_out_n[l_inst]));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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