226 lines
6.6 KiB
Verilog
226 lines
6.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// This is the dac physical interface (drives samples from the low speed clock to the
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// dac clock domain.
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`timescale 1ns/100ps
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module axi_ad9122_if #(
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parameter FPGA_TECHNOLOGY = 0,
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parameter SERDES_OR_DDR_N = 1,
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parameter MMCM_OR_BUFIO_N = 1,
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parameter MMCM_CLKIN_PERIOD = 1.667,
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parameter MMCM_VCO_DIV = 6,
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parameter MMCM_VCO_MUL = 12,
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parameter MMCM_CLK0_DIV = 2,
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parameter MMCM_CLK1_DIV = 8,
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parameter IO_DELAY_GROUP = "dac_if_delay_group"
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) (
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// dac interface
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input dac_clk_in_p,
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input dac_clk_in_n,
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output dac_clk_out_p,
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output dac_clk_out_n,
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output dac_frame_out_p,
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output dac_frame_out_n,
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output [15:0] dac_data_out_p,
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output [15:0] dac_data_out_n,
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// internal resets and clocks
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input dac_rst,
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output dac_clk,
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output dac_div_clk,
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output reg dac_status,
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// data interface
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input dac_frame_i0,
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input [15:0] dac_data_i0,
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input dac_frame_i1,
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input [15:0] dac_data_i1,
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input dac_frame_i2,
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input [15:0] dac_data_i2,
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input dac_frame_i3,
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input [15:0] dac_data_i3,
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input dac_frame_q0,
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input [15:0] dac_data_q0,
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input dac_frame_q1,
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input [15:0] dac_data_q1,
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input dac_frame_q2,
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input [15:0] dac_data_q2,
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input dac_frame_q3,
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input [15:0] dac_data_q3,
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// mmcm reset
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input mmcm_rst,
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// drp interface
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input up_clk,
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input up_rstn,
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input up_drp_sel,
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input up_drp_wr,
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input [11:0] up_drp_addr,
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input [31:0] up_drp_wdata,
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output [31:0] up_drp_rdata,
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output up_drp_ready,
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output up_drp_locked
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);
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// internal registers
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reg dac_status_m1 = 'd0;
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// internal signals
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wire dac_out_clk;
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// dac status
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always @(posedge dac_div_clk) begin
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if (dac_rst == 1'b1) begin
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dac_status_m1 <= 1'd0;
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dac_status <= 1'd0;
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end else begin
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dac_status_m1 <= up_drp_locked;
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dac_status <= dac_status_m1;
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end
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end
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// dac data output serdes(s) & buffers
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ad_serdes_out #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.DDR_OR_SDR_N (SERDES_OR_DDR_N),
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.DATA_WIDTH (16)
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) i_serdes_out_data (
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.rst (dac_rst),
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.clk (dac_clk),
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.div_clk (dac_div_clk),
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.data_oe (1'b1),
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.data_s0 (dac_data_i0),
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.data_s1 (dac_data_q0),
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.data_s2 (dac_data_i1),
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.data_s3 (dac_data_q1),
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.data_s4 (dac_data_i2),
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.data_s5 (dac_data_q2),
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.data_s6 (dac_data_i3),
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.data_s7 (dac_data_q3),
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.data_out_se (),
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.data_out_p (dac_data_out_p),
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.data_out_n (dac_data_out_n));
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// dac frame output serdes & buffer
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ad_serdes_out #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.DDR_OR_SDR_N (SERDES_OR_DDR_N),
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.DATA_WIDTH (1)
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) i_serdes_out_frame (
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.rst (dac_rst),
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.clk (dac_clk),
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.div_clk (dac_div_clk),
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.data_oe (1'b1),
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.data_s0 (dac_frame_i0),
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.data_s1 (dac_frame_q0),
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.data_s2 (dac_frame_i1),
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.data_s3 (dac_frame_q1),
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.data_s4 (dac_frame_i2),
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.data_s5 (dac_frame_q2),
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.data_s6 (dac_frame_i3),
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.data_s7 (dac_frame_q3),
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.data_out_se (),
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.data_out_p (dac_frame_out_p),
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.data_out_n (dac_frame_out_n));
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// dac clock output serdes & buffer
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ad_serdes_out #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.DDR_OR_SDR_N (SERDES_OR_DDR_N),
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.DATA_WIDTH (1)
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) i_serdes_out_clk (
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.rst (dac_rst),
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.clk (dac_clk),
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.div_clk (dac_div_clk),
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.data_oe (1'b1),
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.data_s0 (1'b1),
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.data_s1 (1'b0),
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.data_s2 (1'b1),
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.data_s3 (1'b0),
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.data_s4 (1'b1),
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.data_s5 (1'b0),
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.data_s6 (1'b1),
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.data_s7 (1'b0),
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.data_out_se (),
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.data_out_p (dac_clk_out_p),
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.data_out_n (dac_clk_out_n));
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// dac clock input buffers
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ad_serdes_clk #(
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.DDR_OR_SDR_N (SERDES_OR_DDR_N),
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.MMCM_OR_BUFR_N (MMCM_OR_BUFIO_N),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
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.MMCM_VCO_DIV (MMCM_VCO_DIV),
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.MMCM_VCO_MUL (MMCM_VCO_MUL),
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.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
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.MMCM_CLK1_DIV (MMCM_CLK1_DIV)
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) i_serdes_clk (
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.rst (mmcm_rst),
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.clk_in_p (dac_clk_in_p),
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.clk_in_n (dac_clk_in_n),
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.clk (dac_clk),
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.div_clk (dac_div_clk),
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.out_clk (dac_out_clk),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_drp_sel (up_drp_sel),
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.up_drp_wr (up_drp_wr),
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.up_drp_addr (up_drp_addr),
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.up_drp_wdata (up_drp_wdata),
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.up_drp_rdata (up_drp_rdata),
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.up_drp_ready (up_drp_ready),
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.up_drp_locked (up_drp_locked));
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endmodule
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