105 lines
3.5 KiB
Verilog
105 lines
3.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_ad9361_tdd_if #(
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parameter LEVEL_OR_PULSE_N = 0
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) (
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input clk,
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input rst,
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// control signals from the tdd control
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input tdd_rx_vco_en,
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input tdd_tx_vco_en,
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input tdd_rx_rf_en,
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input tdd_tx_rf_en,
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// device interface
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output ad9361_txnrx,
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output ad9361_enable,
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// interface status
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output [ 7:0] ad9361_tdd_status
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);
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localparam PULSE_MODE = 0;
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localparam LEVEL_MODE = 1;
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// internal registers
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reg tdd_vco_overlap = 1'b0;
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reg tdd_rf_overlap = 1'b0;
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wire ad9361_txnrx_s;
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wire ad9361_enable_s;
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// just one VCO can be enabled at a time
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assign ad9361_txnrx_s = tdd_tx_vco_en & ~tdd_rx_vco_en;
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generate
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if (LEVEL_OR_PULSE_N == PULSE_MODE) begin
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reg tdd_rx_rf_en_d = 1'b0;
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reg tdd_tx_rf_en_d = 1'b0;
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always @(posedge clk) begin
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tdd_rx_rf_en_d <= tdd_rx_rf_en;
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tdd_tx_rf_en_d <= tdd_tx_rf_en;
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end
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assign ad9361_enable_s = (tdd_rx_rf_en_d ^ tdd_rx_rf_en) ||
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(tdd_tx_rf_en_d ^ tdd_tx_rf_en);
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end else
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assign ad9361_enable_s = (tdd_rx_rf_en | tdd_tx_rf_en);
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endgenerate
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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tdd_vco_overlap <= 1'b0;
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tdd_rf_overlap <= 1'b0;
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end else begin
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tdd_vco_overlap <= tdd_rx_vco_en & tdd_tx_vco_en;
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tdd_rf_overlap <= tdd_rx_rf_en & tdd_tx_rf_en;
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end
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end
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assign ad9361_tdd_status = {6'b0, tdd_rf_overlap, tdd_vco_overlap};
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assign ad9361_txnrx = ad9361_txnrx_s;
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assign ad9361_enable = ad9361_enable_s;
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endmodule
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