446 lines
14 KiB
Tcl
446 lines
14 KiB
Tcl
###############################################################################
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## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# ip
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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global VIVADO_IP_LIBRARY
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adi_ip_create axi_dmac
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adi_ip_files axi_dmac [list \
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"$ad_hdl_dir/library/common/ad_mem_asym.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"inc_id.vh" \
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"resp.vh" \
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"axi_dmac_burst_memory.v" \
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"axi_dmac_regmap.v" \
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"axi_dmac_regmap_request.v" \
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"axi_dmac_reset_manager.v" \
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"axi_dmac_resize_dest.v" \
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"axi_dmac_resize_src.v" \
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"axi_dmac_response_manager.v" \
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"axi_dmac_transfer.v" \
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"address_generator.v" \
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"data_mover.v" \
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"request_arb.v" \
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"request_generator.v" \
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"response_handler.v" \
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"axi_register_slice.v" \
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"dmac_2d_transfer.v" \
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"dest_axi_mm.v" \
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"dest_axi_stream.v" \
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"dest_fifo_inf.v" \
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"src_axi_mm.v" \
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"src_axi_stream.v" \
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"src_fifo_inf.v" \
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"splitter.v" \
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"response_generator.v" \
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"axi_dmac.v" \
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"axi_dmac_constr.ttcl" \
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"axi_dmac_pkg_sv.ttcl" \
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"bd/bd.tcl" ]
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adi_ip_properties axi_dmac
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adi_ip_infer_mm_interfaces axi_dmac
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adi_ip_ttcl axi_dmac "axi_dmac_constr.ttcl"
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adi_ip_sim_ttcl axi_dmac "axi_dmac_pkg_sv.ttcl"
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adi_ip_bd axi_dmac "bd/bd.tcl"
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set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_dmac} [ipx::current_core]
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adi_ip_add_core_dependencies [list \
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analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo:1.0 \
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analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
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]
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set_property display_name "ADI AXI DMA Controller" [ipx::current_core]
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set_property description "ADI AXI DMA Controller" [ipx::current_core]
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adi_add_bus "s_axis" "slave" \
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"xilinx.com:interface:axis_rtl:1.0" \
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"xilinx.com:interface:axis:1.0" \
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[list {"s_axis_ready" "TREADY"} \
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{"s_axis_valid" "TVALID"} \
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{"s_axis_data" "TDATA"} \
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{"s_axis_strb" "TSTRB"} \
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{"s_axis_keep" "TKEEP"} \
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{"s_axis_user" "TUSER"} \
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{"s_axis_id" "TID"} \
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{"s_axis_dest" "TDEST"} \
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{"s_axis_last" "TLAST"}]
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adi_add_bus_clock "s_axis_aclk" "s_axis"
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adi_add_bus "m_axis" "master" \
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"xilinx.com:interface:axis_rtl:1.0" \
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"xilinx.com:interface:axis:1.0" \
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[list {"m_axis_ready" "TREADY"} \
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{"m_axis_valid" "TVALID"} \
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{"m_axis_data" "TDATA"} \
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{"m_axis_strb" "TSTRB"} \
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{"m_axis_keep" "TKEEP"} \
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{"m_axis_user" "TUSER"} \
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{"m_axis_id" "TID"} \
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{"m_axis_dest" "TDEST"} \
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{"m_axis_last" "TLAST"}]
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adi_add_bus_clock "m_axis_aclk" "m_axis"
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adi_set_bus_dependency "m_src_axi" "m_src_axi" \
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 0)"
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adi_set_bus_dependency "m_dest_axi" "m_dest_axi" \
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 0)"
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adi_set_bus_dependency "s_axis" "s_axis" \
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 1)"
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adi_set_bus_dependency "m_axis" "m_axis" \
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 1)"
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adi_set_ports_dependency "fifo_rd" \
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 2)"
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adi_set_ports_dependency "dest_diag_level_bursts" \
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"(spirit:decode(id('MODELPARAM_VALUE.ENABLE_DIAGNOSTICS_IF')) = 1)"
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# These are in the design to keep the Intel tools happy which can't handle
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# uni-directional AXI interfaces. The Xilinx tools can and do a better job when
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# they know that the interface is uni-directional, so disable the ports.
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set dummy_axi_ports [list \
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"m_dest_axi_arvalid" \
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"m_dest_axi_arready" \
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"m_dest_axi_araddr" \
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"m_dest_axi_arlen" \
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"m_dest_axi_arsize" \
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"m_dest_axi_arburst" \
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"m_dest_axi_arcache" \
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"m_dest_axi_arprot" \
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"m_dest_axi_rready" \
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"m_dest_axi_rvalid" \
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"m_dest_axi_rresp" \
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"m_dest_axi_rdata" \
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"m_src_axi_awvalid" \
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"m_src_axi_awready" \
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"m_src_axi_awvalid" \
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"m_src_axi_awaddr" \
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"m_src_axi_awlen" \
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"m_src_axi_awsize" \
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"m_src_axi_awburst" \
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"m_src_axi_awcache" \
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"m_src_axi_awprot" \
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"m_src_axi_wvalid" \
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"m_src_axi_wready" \
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"m_src_axi_wvalid" \
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"m_src_axi_wdata" \
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"m_src_axi_wstrb" \
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"m_src_axi_wlast" \
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"m_src_axi_bready" \
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"m_src_axi_bvalid" \
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"m_src_axi_bresp" \
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]
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# These are in the design to keep the Intel tools happy which require
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# certain signals in AXI3 mode even if these are defined as optinal in the standard.
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lappend dummy_axi_ports \
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"m_dest_axi_awid" \
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"m_dest_axi_awlock" \
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"m_dest_axi_wid" \
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"m_dest_axi_bid" \
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"m_dest_axi_arid" \
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"m_dest_axi_arlock" \
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"m_dest_axi_rid" \
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"m_dest_axi_rlast" \
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"m_src_axi_arid" \
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"m_src_axi_arlock" \
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"m_src_axi_rid" \
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"m_src_axi_awid" \
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"m_src_axi_awlock" \
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"m_src_axi_wid" \
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"m_src_axi_bid"
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foreach p $dummy_axi_ports {
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adi_set_ports_dependency $p "false"
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}
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set_property master_address_space_ref m_dest_axi \
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[ipx::get_bus_interfaces m_dest_axi \
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-of_objects [ipx::current_core]]
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set_property master_address_space_ref m_src_axi \
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[ipx::get_bus_interfaces m_src_axi \
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-of_objects [ipx::current_core]]
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adi_add_bus "fifo_wr" "slave" \
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"analog.com:interface:fifo_wr_rtl:1.0" \
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"analog.com:interface:fifo_wr:1.0" \
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{ \
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{"fifo_wr_en" "EN"} \
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{"fifo_wr_din" "DATA"} \
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{"fifo_wr_overflow" "OVERFLOW"} \
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{"fifo_wr_sync" "SYNC"} \
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{"fifo_wr_xfer_req" "XFER_REQ"} \
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}
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adi_add_bus_clock "fifo_wr_clk" "fifo_wr"
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adi_set_bus_dependency "fifo_wr" "fifo_wr" \
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 2)"
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adi_add_bus "fifo_rd" "slave" \
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"analog.com:interface:fifo_rd_rtl:1.0" \
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"analog.com:interface:fifo_rd:1.0" \
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{
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{"fifo_rd_en" "EN"} \
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{"fifo_rd_dout" "DATA"} \
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{"fifo_rd_valid" "VALID"} \
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{"fifo_rd_underflow" "UNDERFLOW"} \
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}
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adi_add_bus_clock "fifo_rd_clk" "fifo_rd"
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adi_set_bus_dependency "fifo_rd" "fifo_rd" \
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 2)"
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foreach port {"m_dest_axi_aresetn" "m_src_axi_aresetn" \
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"s_axis_valid" "s_axis_data" "s_axis_last" "m_axis_ready" \
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"fifo_wr_en" "fifo_wr_din" "fifo_rd_en"} {
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set_property DRIVER_VALUE "0" [ipx::get_ports $port]
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}
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foreach port {"s_axis_user" "fifo_wr_sync"} {
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set_property DRIVER_VALUE "1" [ipx::get_ports $port]
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}
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# Infer interrupt
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ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
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set cc [ipx::current_core]
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# The core does not issue narrow bursts
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foreach intf [ipx::get_bus_interfaces m_*_axi -of_objects $cc] {
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set para [ipx::add_bus_parameter SUPPORTS_NARROW_BURST $intf]
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set_property "VALUE" "0" $para
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}
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set_property -dict [list \
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"value_validation_type" "list" \
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"value_validation_list" "2 4 8 16 32" \
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] \
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[ipx::get_user_parameters FIFO_SIZE -of_objects $cc]
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set_property -dict [list \
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"value_validation_type" "range_long" \
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"value_validation_range_minimum" "8" \
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"value_validation_range_maximum" "32" \
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] \
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[ipx::get_user_parameters DMA_LENGTH_WIDTH -of_objects $cc]
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set_property -dict [list \
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"value_validation_type" "range_long" \
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"value_validation_range_minimum" "16" \
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"value_validation_range_maximum" "64" \
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] \
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[ipx::get_user_parameters DMA_AXI_ADDR_WIDTH -of_objects $cc]
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foreach {k v} { \
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"ASYNC_CLK_REQ_SRC" "true" \
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"ASYNC_CLK_SRC_DEST" "true" \
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"ASYNC_CLK_DEST_REQ" "true" \
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"CYCLIC" "false" \
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"DMA_2D_TRANSFER" "false" \
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"SYNC_TRANSFER_START" "false" \
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"AXI_SLICE_SRC" "false" \
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"AXI_SLICE_DEST" "false" \
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"DISABLE_DEBUG_REGISTERS" "false" \
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"ENABLE_DIAGNOSTICS_IF" "false" \
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"CACHE_COHERENT_DEST" "false" \
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} { \
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set_property -dict [list \
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"value_format" "bool" \
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"value" $v \
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] \
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[ipx::get_user_parameters $k -of_objects $cc]
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set_property -dict [list \
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"value_format" "bool" \
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"value" $v \
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] \
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[ipx::get_hdl_parameters $k -of_objects $cc]
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}
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set_property -dict [list \
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"enablement_tcl_expr" "\$DMA_TYPE_SRC != 0" \
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] \
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[ipx::get_user_parameters SYNC_TRANSFER_START -of_objects $cc]
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foreach dir {"SRC" "DEST"} {
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set_property -dict [list \
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"value_validation_type" "list" \
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"value_validation_list" "16 32 64 128 256 512 1024 2048" \
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] \
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[ipx::get_user_parameters DMA_DATA_WIDTH_${dir} -of_objects $cc]
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set_property -dict [list \
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"value_validation_type" "pairs" \
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"value_validation_pairs" {"AXI3" "1" "AXI4" "0"} \
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"enablement_tcl_expr" "\$DMA_TYPE_${dir} == 0" \
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] \
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[ipx::get_user_parameters DMA_AXI_PROTOCOL_${dir} -of_objects $cc]
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set_property -dict [list \
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"value_validation_type" "pairs" \
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"value_validation_pairs" { \
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"Memory-Mapped AXI" "0" \
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"Streaming AXI" "1" \
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"FIFO Interface" "2" \
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} \
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] \
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[ipx::get_user_parameters DMA_TYPE_${dir} -of_objects $cc]
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}
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set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
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set g [ipgui::add_group -name {DMA Endpoint Configuration} -component $cc \
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-parent $page0 -display_name {DMA Endpoint Configuration} \
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-layout "horizontal"]
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set src_group [ipgui::add_group -name {Source} -component $cc -parent $g \
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-display_name {Source}]
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set dest_group [ipgui::add_group -name {Destination} -component $cc -parent $g \
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-display_name {Destination}]
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foreach {dir group} [list "SRC" $src_group "DEST" $dest_group] {
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set p [ipgui::get_guiparamspec -name "DMA_TYPE_${dir}" -component $cc]
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ipgui::move_param -component $cc -order 0 $p -parent $group
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set_property -dict [list \
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"widget" "comboBox" \
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"display_name" "Type" \
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] $p
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set p [ipgui::get_guiparamspec -name "DMA_AXI_PROTOCOL_${dir}" -component $cc]
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ipgui::move_param -component $cc -order 1 $p -parent $group
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set_property -dict [list \
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"widget" "comboBox" \
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"display_name" "AXI Protocol" \
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] $p
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set p [ipgui::get_guiparamspec -name "DMA_DATA_WIDTH_${dir}" -component $cc]
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ipgui::move_param -component $cc -order 2 $p -parent $group
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set_property -dict [list \
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"display_name" "Bus Width" \
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"tooltip" "Bus Width: For Memory-Mapped interface the valid range is 32-1024 bits" \
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] $p
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set p [ipgui::get_guiparamspec -name "AXI_SLICE_${dir}" -component $cc]
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ipgui::move_param -component $cc -order 3 $p -parent $group
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set_property -dict [list \
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"display_name" "Insert Register Slice" \
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] $p
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}
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set p [ipgui::get_guiparamspec -name "SYNC_TRANSFER_START" -component $cc]
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ipgui::move_param -component $cc -order 4 $p -parent $src_group
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set_property -dict [list \
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"display_name" "Transfer Start Synchronization Support" \
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] $p
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set p [ipgui::get_guiparamspec -name "CACHE_COHERENT_DEST" -component $cc]
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ipgui::move_param -component $cc -order 4 $p -parent $dest_group
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set_property -dict [list \
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"tooltip" "Assume destination port ensures cache coherency (e.g. Ultrascale HPC port)" \
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] $p
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set_property -dict [list \
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"display_name" "Assume cache coherent" \
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"enablement_tcl_expr" "\$DMA_TYPE_DEST == 0 && \$DMA_AXI_PROTOCOL_DEST == 0" \
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"value_tcl_expr" "\$DMA_TYPE_DEST == 0 && \$DMA_AXI_PROTOCOL_DEST == 0" \
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"enablement_value" "false" \
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] [ipx::get_user_parameters CACHE_COHERENT_DEST -of_objects $cc]
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set general_group [ipgui::add_group -name "General Configuration" -component $cc \
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-parent $page0 -display_name "General Configuration"]
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set p [ipgui::get_guiparamspec -name "ID" -component $cc]
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ipgui::move_param -component $cc -order 0 $p -parent $general_group
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set_property -dict [list \
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"display_name" "Core ID" \
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] $p
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set p [ipgui::get_guiparamspec -name "DMA_LENGTH_WIDTH" -component $cc]
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ipgui::move_param -component $cc -order 1 $p -parent $general_group
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set_property -dict [list \
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"display_name" "DMA Transfer Length Register Width" \
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] $p
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set p [ipgui::get_guiparamspec -name "FIFO_SIZE" -component $cc]
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ipgui::move_param -component $cc -order 2 $p -parent $general_group
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set_property -dict [list \
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"widget" "comboBox" \
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"display_name" "Store-and-Forward Memory Size (In Bursts)" \
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] $p
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set p [ipgui::get_guiparamspec -name "MAX_BYTES_PER_BURST" -component $cc]
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ipgui::move_param -component $cc -order 3 $p -parent $general_group
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set_property -dict [list \
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"display_name" "Maximum Bytes per Burst" \
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] $p
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set p [ipgui::get_guiparamspec -name "DMA_AXI_ADDR_WIDTH" -component $cc]
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ipgui::move_param -component $cc -order 4 $p -parent $general_group
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set_property -dict [list \
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"display_name" "DMA AXI Address Width" \
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] $p
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set feature_group [ipgui::add_group -name "Features" -component $cc \
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-parent $page0 -display_name "Features"]
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set p [ipgui::get_guiparamspec -name "CYCLIC" -component $cc]
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ipgui::move_param -component $cc -order 0 $p -parent $feature_group
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set_property -dict [list \
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"display_name" "Cyclic Transfer Support" \
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] $p
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set p [ipgui::get_guiparamspec -name "DMA_2D_TRANSFER" -component $cc]
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ipgui::move_param -component $cc -order 1 $p -parent $feature_group
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set_property -dict [list \
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"display_name" "2D Transfer Support" \
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] $p
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set clk_group [ipgui::add_group -name {Clock Domain Configuration} -component $cc \
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-parent $page0 -display_name {Clock Domain Configuration}]
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set p [ipgui::get_guiparamspec -name "ASYNC_CLK_REQ_SRC" -component $cc]
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ipgui::move_param -component $cc -order 0 $p -parent $clk_group
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set_property -dict [list \
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"display_name" "Request and Source Clock Asynchronous" \
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] $p
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set p [ipgui::get_guiparamspec -name "ASYNC_CLK_SRC_DEST" -component $cc]
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ipgui::move_param -component $cc -order 1 $p -parent $clk_group
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|
set_property -dict [list \
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|
"display_name" "Source and Destination Clock Asynchronous" \
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|
] $p
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|
|
|
set p [ipgui::get_guiparamspec -name "ASYNC_CLK_DEST_REQ" -component $cc]
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|
ipgui::move_param -component $cc -order 2 $p -parent $clk_group
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|
set_property -dict [list \
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|
"display_name" "Destination and Request Clock Asynchronous" \
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|
] $p
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|
|
|
set dbg_group [ipgui::add_group -name {Debug} -component $cc \
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|
-parent $page0 -display_name {Debug}]
|
|
|
|
set p [ipgui::get_guiparamspec -name "DISABLE_DEBUG_REGISTERS" -component $cc]
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|
ipgui::move_param -component $cc -order 0 $p -parent $dbg_group
|
|
set_property -dict [list \
|
|
"display_name" "Disable Debug Registers" \
|
|
] $p
|
|
|
|
set p [ipgui::get_guiparamspec -name "ENABLE_DIAGNOSTICS_IF" -component $cc]
|
|
ipgui::move_param -component $cc -order 1 $p -parent $dbg_group
|
|
set_property -dict [list \
|
|
"display_name" "Enable Diagnostics Interface" \
|
|
] $p
|
|
|
|
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_SRC" -component $cc]
|
|
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_DEST" -component $cc]
|
|
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "ALLOW_ASYM_MEM" -component $cc]
|
|
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXIS_ID_W" -component $cc]
|
|
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXIS_DEST_W" -component $cc]
|
|
|
|
ipx::create_xgui_files [ipx::current_core]
|
|
ipx::save_core $cc
|