307 lines
9.7 KiB
Verilog
307 lines
9.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dmac_regmap #(
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parameter ID = 0,
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parameter DISABLE_DEBUG_REGISTERS = 0,
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parameter BYTES_PER_BEAT_WIDTH_DEST = 1,
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parameter BYTES_PER_BEAT_WIDTH_SRC = 1,
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parameter BYTES_PER_BURST_WIDTH = 7,
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parameter DMA_TYPE_DEST = 0,
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parameter DMA_TYPE_SRC = 2,
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parameter DMA_AXI_ADDR_WIDTH = 32,
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parameter DMA_LENGTH_WIDTH = 24,
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parameter DMA_LENGTH_ALIGN = 3,
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parameter DMA_CYCLIC = 0,
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parameter HAS_DEST_ADDR = 1,
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parameter HAS_SRC_ADDR = 1,
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parameter DMA_2D_TRANSFER = 0,
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parameter SYNC_TRANSFER_START = 0,
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parameter CACHE_COHERENT_DEST = 0
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) (
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// Slave AXI interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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output s_axi_awready,
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input [10:0] s_axi_awaddr,
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input [2:0] s_axi_awprot,
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input s_axi_wvalid,
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output s_axi_wready,
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input [31:0] s_axi_wdata,
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input [3:0] s_axi_wstrb,
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output s_axi_bvalid,
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input s_axi_bready,
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output [1:0] s_axi_bresp,
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input s_axi_arvalid,
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output s_axi_arready,
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input [10:0] s_axi_araddr,
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input [2:0] s_axi_arprot,
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output s_axi_rvalid,
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input s_axi_rready,
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output [1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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// Interrupt
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output reg irq,
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// Control interface
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output reg ctrl_enable = 1'b0,
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output reg ctrl_pause = 1'b0,
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// DMA request interface
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output request_valid,
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input request_ready,
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output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] request_dest_address,
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output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] request_src_address,
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output [DMA_LENGTH_WIDTH-1:0] request_x_length,
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output [DMA_LENGTH_WIDTH-1:0] request_y_length,
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output [DMA_LENGTH_WIDTH-1:0] request_dest_stride,
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output [DMA_LENGTH_WIDTH-1:0] request_src_stride,
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output request_sync_transfer_start,
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output request_last,
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// DMA response interface
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input response_eot,
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input [BYTES_PER_BURST_WIDTH-1:0] response_measured_burst_length,
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input response_partial,
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input response_valid,
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output response_ready,
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// Debug interface
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input [DMA_AXI_ADDR_WIDTH-1:0] dbg_src_addr,
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input [DMA_AXI_ADDR_WIDTH-1:0] dbg_dest_addr,
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input [11:0] dbg_status,
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input [31:0] dbg_ids0,
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input [31:0] dbg_ids1
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);
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localparam PCORE_VERSION = 'h00040461;
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localparam HAS_ADDR_HIGH = DMA_AXI_ADDR_WIDTH > 32;
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localparam ADDR_LOW_MSB = HAS_ADDR_HIGH ? 31 : DMA_AXI_ADDR_WIDTH-1;
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// Register interface signals
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reg [31:0] up_rdata = 32'h00;
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reg up_wack = 1'b0;
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reg up_rack = 1'b0;
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wire up_wreq;
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wire up_rreq;
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wire [31:0] up_wdata;
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wire [8:0] up_waddr;
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wire [8:0] up_raddr;
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wire [31:0] up_rdata_request;
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// Scratch register
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reg [31:0] up_scratch = 32'h00;
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// Start and end of transfer
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wire up_eot; // Asserted for one cycle when a transfer has been completed
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wire up_sot; // Asserted for one cycle when a transfer has been queued
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// Interupt handling
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reg [1:0] up_irq_mask = 2'h3;
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reg [1:0] up_irq_source = 2'h0;
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wire [1:0] up_irq_pending;
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wire [1:0] up_irq_trigger;
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wire [1:0] up_irq_source_clear;
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// IRQ handling
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assign up_irq_pending = ~up_irq_mask & up_irq_source;
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assign up_irq_trigger = {up_eot, up_sot};
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assign up_irq_source_clear = (up_wreq == 1'b1 && up_waddr == 9'h021) ? up_wdata[1:0] : 2'b00;
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always @(posedge s_axi_aclk) begin
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if (s_axi_aresetn == 1'b0) begin
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irq <= 1'b0;
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end else begin
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irq <= |up_irq_pending;
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end
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end
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always @(posedge s_axi_aclk) begin
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if (s_axi_aresetn == 1'b0) begin
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up_irq_source <= 2'b00;
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end else begin
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up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear);
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end
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end
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// Register Interface
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always @(posedge s_axi_aclk) begin
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if (s_axi_aresetn == 1'b0) begin
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ctrl_enable <= 1'b0;
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ctrl_pause <= 1'b0;
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up_irq_mask <= 2'b11;
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up_scratch <= 32'h00;
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up_wack <= 1'b0;
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end else begin
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up_wack <= up_wreq;
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if (up_wreq == 1'b1) begin
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case (up_waddr)
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9'h002: up_scratch <= up_wdata;
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9'h020: up_irq_mask <= up_wdata[1:0];
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9'h100: {ctrl_pause, ctrl_enable} <= up_wdata[1:0];
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endcase
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end
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end
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end
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always @(posedge s_axi_aclk) begin
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if (s_axi_aresetn == 1'b0) begin
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up_rack <= 'd0;
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end else begin
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up_rack <= up_rreq;
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end
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end
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always @(posedge s_axi_aclk) begin
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if (up_rreq == 1'b1) begin
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case (up_raddr)
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9'h000: up_rdata <= PCORE_VERSION;
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9'h001: up_rdata <= ID;
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9'h002: up_rdata <= up_scratch;
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9'h003: up_rdata <= 32'h444d4143; // "DMAC"
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9'h004: up_rdata <= {8'b0,
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4'b0,BYTES_PER_BURST_WIDTH[3:0],
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2'b0,DMA_TYPE_SRC[1:0],BYTES_PER_BEAT_WIDTH_SRC[3:0],
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2'b0,DMA_TYPE_DEST[1:0],BYTES_PER_BEAT_WIDTH_DEST[3:0]};
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9'h005: up_rdata <= {31'd0, CACHE_COHERENT_DEST};
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9'h020: up_rdata <= up_irq_mask;
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9'h021: up_rdata <= up_irq_pending;
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9'h022: up_rdata <= up_irq_source;
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9'h100: up_rdata <= {ctrl_pause, ctrl_enable};
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9'h10d: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_dest_addr[ADDR_LOW_MSB:0];
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9'h10e: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_src_addr[ADDR_LOW_MSB:0];
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9'h10f: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_status;
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9'h110: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids0;
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9'h111: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids1;
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9'h126: up_rdata <= (HAS_ADDR_HIGH && !DISABLE_DEBUG_REGISTERS) ? dbg_dest_addr[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
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9'h127: up_rdata <= (HAS_ADDR_HIGH && !DISABLE_DEBUG_REGISTERS) ? dbg_src_addr[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
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default: up_rdata <= up_rdata_request;
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endcase
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end
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end
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axi_dmac_regmap_request #(
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.DISABLE_DEBUG_REGISTERS(DISABLE_DEBUG_REGISTERS),
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.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
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.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
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.BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
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.DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
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.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
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.DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN),
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.DMA_CYCLIC(DMA_CYCLIC),
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.HAS_DEST_ADDR(HAS_DEST_ADDR),
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.HAS_SRC_ADDR(HAS_SRC_ADDR),
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.DMA_2D_TRANSFER(DMA_2D_TRANSFER),
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.SYNC_TRANSFER_START(SYNC_TRANSFER_START)
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) i_regmap_request (
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.clk(s_axi_aclk),
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.reset(~s_axi_aresetn),
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.up_sot(up_sot),
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.up_eot(up_eot),
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.up_wreq(up_wreq),
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.up_rreq(up_rreq),
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.up_waddr(up_waddr),
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.up_wdata(up_wdata),
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.up_raddr(up_raddr),
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.up_rdata(up_rdata_request),
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.ctrl_enable(ctrl_enable),
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.request_valid(request_valid),
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.request_ready(request_ready),
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.request_dest_address(request_dest_address),
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.request_src_address(request_src_address),
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.request_x_length(request_x_length),
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.request_y_length(request_y_length),
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.request_dest_stride(request_dest_stride),
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.request_src_stride(request_src_stride),
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.request_sync_transfer_start(request_sync_transfer_start),
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.request_last(request_last),
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.response_eot(response_eot),
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.response_measured_burst_length(response_measured_burst_length),
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.response_partial(response_partial),
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.response_valid(response_valid),
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.response_ready(response_ready));
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up_axi #(
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.AXI_ADDRESS_WIDTH (11)
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) i_up_axi (
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.up_rstn(s_axi_aresetn),
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.up_clk(s_axi_aclk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
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.up_axi_wready(s_axi_wready),
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.up_axi_bvalid(s_axi_bvalid),
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.up_axi_bresp(s_axi_bresp),
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.up_axi_bready(s_axi_bready),
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.up_axi_arvalid(s_axi_arvalid),
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.up_axi_araddr(s_axi_araddr),
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.up_axi_arready(s_axi_arready),
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.up_axi_rvalid(s_axi_rvalid),
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_wreq(up_wreq),
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.up_waddr(up_waddr),
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.up_wdata(up_wdata),
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.up_wack(up_wack),
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.up_rreq(up_rreq),
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.up_raddr(up_raddr),
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.up_rdata(up_rdata),
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.up_rack(up_rack));
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endmodule
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