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axi_read_slave.v
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2023-07-11 15:17:41 +03:00 |
axi_slave.v
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2023-07-11 15:17:41 +03:00 |
axi_write_slave.v
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2023-07-11 15:17:41 +03:00 |
dma_read_shutdown_tb
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library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer
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2022-04-01 16:02:46 +03:00 |
dma_read_shutdown_tb.v
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2023-07-11 15:17:41 +03:00 |
dma_read_tb
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library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer
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2022-04-01 16:02:46 +03:00 |
dma_read_tb.v
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2023-07-11 15:17:41 +03:00 |
dma_write_shutdown_tb
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library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer
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2022-04-01 16:02:46 +03:00 |
dma_write_shutdown_tb.v
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2023-07-11 15:17:41 +03:00 |
dma_write_tb
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library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer
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2022-04-01 16:02:46 +03:00 |
dma_write_tb.v
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2023-07-11 15:17:41 +03:00 |
regmap_tb
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Testbenches: Unify and optimize HDL testbenches
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2021-05-07 19:53:14 +03:00 |
regmap_tb.v
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2023-07-11 15:17:41 +03:00 |
reset_manager_tb
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Testbenches: Unify and optimize HDL testbenches
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2021-05-07 19:53:14 +03:00 |
reset_manager_tb.v
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2023-07-11 15:17:41 +03:00 |
tb_base.v
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2023-07-11 15:17:41 +03:00 |