322 lines
10 KiB
Verilog
322 lines
10 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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/* This module controls the read and write access to the storage unit. It is
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* used for both transmit and receive use cases
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*/
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module data_offload_fsm #(
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parameter TX_OR_RXN_PATH = 0,
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parameter SYNC_EXT_ADD_INTERNAL_CDC = 1
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) (
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input up_clk,
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// Control interface for storage for m_storage_axis interface
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output reg wr_request_enable = 1'b0,
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output wr_request_valid,
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input wr_request_ready,
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input wr_response_eot,
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// Control interface for storage for s_storage_axis interface
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output reg rd_request_enable = 1'b0,
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output rd_request_valid,
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input rd_request_ready,
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input rd_response_eot,
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input rd_ml_valid,
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output rd_ml_ready,
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// Data path gating
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output wr_ready,
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output rd_ready,
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input rd_valid,
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// write control interface
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input wr_clk,
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input wr_resetn_in,
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input wr_bypass,
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// read control interface
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input rd_clk,
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input rd_resetn_in,
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input rd_oneshot, // 0 - CYCLIC; 1 - ONE_SHOT;
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// Synchronization interface - synchronous to the external DMA clock
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input init_req,
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input [ 1:0] sync_config,
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input sync_external,
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input sync_internal,
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// FSM debug
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output [ 4:0] wr_fsm_state_out,
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output [ 3:0] rd_fsm_state_out
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);
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// FSM states
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localparam WR_STATE_IDLE = 5'b00001;
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localparam WR_STATE_PRE_WR = 5'b00010;
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localparam WR_STATE_SYNC = 5'b00100;
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localparam WR_STATE_WR = 5'b01000;
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localparam WR_STATE_WAIT_RD = 5'b10000;
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localparam WR_BIT_IDLE = 0;
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localparam WR_BIT_PRE_WR = 1;
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localparam WR_BIT_SYNC = 2;
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localparam WR_BIT_WR = 3;
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localparam RD_STATE_IDLE = 4'b0001;
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localparam RD_STATE_PRE_RD = 4'b0010;
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localparam RD_STATE_SYNC = 4'b0100;
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localparam RD_STATE_RD = 4'b1000;
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localparam RD_BIT_IDLE = 0;
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localparam RD_BIT_PRE_RD = 1;
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localparam RD_BIT_SYNC = 2;
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localparam RD_BIT_RD = 3;
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// Synchronization options
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localparam AUTOMATIC = 2'b00;
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localparam HARDWARE = 2'b01;
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localparam SOFTWARE = 2'b10;
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// internal registers
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reg rd_cyclic_en = 1'b0;
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// internal signals
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wire wr_sync_external_s;
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wire wr_init_req_s;
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wire wr_rd_response_eot;
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wire rd_sync_external_s;
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wire rd_last_eot;
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wire rd_init_req_s;
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reg [4:0] wr_fsm_state = WR_STATE_IDLE;
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reg [4:0] wr_fsm_next_state;
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reg [3:0] rd_fsm_state = RD_STATE_IDLE;
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reg [3:0] rd_fsm_next_state;
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reg [1:0] rd_outstanding = 2'd0;
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assign wr_fsm_state_out = wr_fsm_state;
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assign rd_fsm_state_out = rd_fsm_state;
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always @(*) begin
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wr_fsm_next_state = wr_fsm_state;
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case (wr_fsm_state)
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WR_STATE_IDLE:
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if (wr_init_req_s & ~wr_bypass) begin
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wr_fsm_next_state = WR_STATE_PRE_WR;
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end
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WR_STATE_PRE_WR:
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if (wr_request_ready) begin
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wr_fsm_next_state = TX_OR_RXN_PATH ? WR_STATE_WR : WR_STATE_SYNC;
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end
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WR_STATE_SYNC:
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case (sync_config)
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AUTOMATIC:
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wr_fsm_next_state = WR_STATE_WR;
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HARDWARE:
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if (wr_sync_external_s) begin
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wr_fsm_next_state = WR_STATE_WR;
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end
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SOFTWARE:
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if (sync_internal) begin
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wr_fsm_next_state = WR_STATE_WR;
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end
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default:
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wr_fsm_next_state = WR_STATE_WR;
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endcase
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WR_STATE_WR:
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if (wr_response_eot) begin
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wr_fsm_next_state = WR_STATE_WAIT_RD;
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end
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WR_STATE_WAIT_RD:
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if (wr_rd_response_eot) begin
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wr_fsm_next_state = WR_STATE_IDLE;
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end
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default:
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wr_fsm_next_state = WR_STATE_IDLE;
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endcase
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end
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always @(posedge wr_clk) begin
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if (wr_resetn_in == 1'b0) begin
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wr_fsm_state <= WR_STATE_IDLE;
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end else begin
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wr_fsm_state <= wr_fsm_next_state;
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end
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end
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always @(*) begin
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rd_fsm_next_state = rd_fsm_state;
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case (rd_fsm_state)
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RD_STATE_IDLE:
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if (rd_ml_valid) begin
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rd_fsm_next_state = RD_STATE_PRE_RD;
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end
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RD_STATE_PRE_RD:
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if (rd_request_ready) begin
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rd_fsm_next_state = TX_OR_RXN_PATH ? RD_STATE_SYNC : RD_STATE_RD;
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end
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RD_STATE_SYNC:
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if (rd_valid) // Wait until storage is valid
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case (sync_config)
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AUTOMATIC:
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rd_fsm_next_state = RD_STATE_RD;
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HARDWARE:
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if (rd_sync_external_s) begin
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rd_fsm_next_state = RD_STATE_RD;
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end
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SOFTWARE:
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if (sync_internal) begin
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rd_fsm_next_state = RD_STATE_RD;
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end
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default:
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rd_fsm_next_state = RD_STATE_RD;
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endcase
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RD_STATE_RD:
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if (rd_last_eot) begin
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rd_fsm_next_state = (rd_cyclic_en == 1'b0) ? RD_STATE_IDLE :
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(TX_OR_RXN_PATH & (sync_config != AUTOMATIC)) ? RD_STATE_SYNC :
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RD_STATE_RD;
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end
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default:
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rd_fsm_next_state = RD_STATE_IDLE;
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endcase
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end
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always @(posedge rd_clk) begin
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if (rd_resetn_in == 1'b0) begin
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rd_fsm_state <= RD_STATE_IDLE;
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end else begin
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rd_fsm_state <= rd_fsm_next_state;
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end
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end
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always @(posedge rd_clk) begin
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if (rd_resetn_in == 1'b0)
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rd_outstanding <= 2'b0;
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else if (rd_request_ready & rd_request_valid & ~rd_response_eot)
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rd_outstanding <= rd_outstanding + 2'd1;
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else if (~(rd_request_ready & rd_request_valid) & (rd_response_eot & rd_fsm_state[RD_BIT_RD]))
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rd_outstanding <= rd_outstanding - 2'd1;
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end
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assign rd_last_eot = (rd_outstanding == 1) & (rd_response_eot & rd_fsm_state[RD_BIT_RD]) & !(rd_request_ready & rd_request_valid);
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always @(posedge rd_clk) begin
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if (rd_init_req_s) begin
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rd_cyclic_en <= 1'b0;
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end else if (rd_fsm_state[RD_BIT_PRE_RD]) begin
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rd_cyclic_en <= ~rd_oneshot;
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end
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end
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assign rd_ready = rd_fsm_state[RD_BIT_RD];
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assign wr_ready = wr_fsm_state[WR_BIT_WR];
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assign wr_request_valid = wr_fsm_state[WR_BIT_PRE_WR];
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assign rd_request_valid = rd_fsm_state[RD_BIT_PRE_RD] | rd_cyclic_en;
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always @(posedge rd_clk) begin
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if (rd_resetn_in == 1'b0 || (~rd_init_req_s & ~TX_OR_RXN_PATH[0]))
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rd_request_enable <= 1'b0;
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else
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rd_request_enable <= 1'b1;
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end
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always @(posedge wr_clk) begin
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if (wr_resetn_in == 1'b0)
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wr_request_enable <= 1'b0;
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else
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wr_request_enable <= 1'b1;
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end
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assign rd_ml_ready = rd_fsm_state[RD_BIT_IDLE];
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// CDC circuits
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sync_event #(
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.NUM_OF_EVENTS (1),
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.ASYNC_CLK (1)
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) i_wr_empty_sync (
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.in_clk (rd_clk),
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.in_event (rd_last_eot && rd_fsm_state[RD_BIT_RD]),
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.out_clk (wr_clk),
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.out_event (wr_rd_response_eot));
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sync_bits #(
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.NUM_OF_BITS (1),
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.ASYNC_CLK (TX_OR_RXN_PATH[0])
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) i_rd_init_req_sync (
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.in_bits (init_req),
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.out_clk (rd_clk),
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.out_resetn (1'b1),
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.out_bits (rd_init_req_s));
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sync_bits #(
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.NUM_OF_BITS (1),
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.ASYNC_CLK (~TX_OR_RXN_PATH[0])
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) i_wr_init_req_sync (
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.in_bits (init_req),
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.out_clk (wr_clk),
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.out_resetn (1'b1),
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.out_bits (wr_init_req_s));
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// When SYNC_EXT_ADD_INTERNAL_CDC is deasserted, one of these signals will end
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// up being synchronized to the "wrong" clock domain. This shouldn't matter
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// because the incorrectly synchronized signal is guarded by a synthesis constant.
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sync_bits #(
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.NUM_OF_BITS (1),
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.ASYNC_CLK (SYNC_EXT_ADD_INTERNAL_CDC)
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) i_sync_wr_sync (
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.in_bits ({ sync_external }),
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.out_clk (wr_clk),
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.out_resetn (1'b1),
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.out_bits ({wr_sync_external_s}));
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sync_bits #(
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.NUM_OF_BITS (1),
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.ASYNC_CLK (SYNC_EXT_ADD_INTERNAL_CDC)
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) i_sync_rd_sync (
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.in_bits ({ sync_external }),
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.out_clk (rd_clk),
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.out_resetn (1'b1),
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.out_bits ({ rd_sync_external_s }));
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endmodule
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