143 lines
3.2 KiB
Verilog
143 lines
3.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module elastic_buffer #(
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parameter IWIDTH = 32,
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parameter OWIDTH = 48,
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parameter SIZE = 256,
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parameter ASYNC_CLK = 0
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) (
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input clk,
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input reset,
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input device_clk,
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input device_reset,
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input [IWIDTH-1:0] wr_data,
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output [OWIDTH-1:0] rd_data,
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input ready_n,
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input do_release_n
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);
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localparam ADDR_WIDTH = SIZE > 128 ? 7 :
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SIZE > 64 ? 6 :
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SIZE > 32 ? 5 :
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SIZE > 16 ? 4 :
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SIZE > 8 ? 3 :
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SIZE > 4 ? 2 :
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SIZE > 2 ? 1 : 0;
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localparam WIDTH = OWIDTH >= IWIDTH ? OWIDTH : IWIDTH;
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reg [ADDR_WIDTH:0] wr_addr = 'h00;
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reg [ADDR_WIDTH:0] rd_addr = 'h00;
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(* ram_style = "distributed" *) reg [WIDTH-1:0] mem[0:SIZE - 1];
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reg mem_rd_valid = 'b0;
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reg [WIDTH-1:0] mem_rd_data;
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wire mem_wr;
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wire [WIDTH-1:0] mem_wr_data;
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wire unpacker_ready;
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generate if ((OWIDTH < IWIDTH) && ASYNC_CLK) begin
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assign mem_wr = 1'b1;
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always @(posedge clk) begin
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if (ready_n) begin
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wr_addr <= 'h00;
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end else if (mem_wr) begin
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wr_addr <= wr_addr + 1;
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end
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end
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always @(posedge clk) begin
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if (mem_wr) begin
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mem[wr_addr] <= wr_data;
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end
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end
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assign mem_rd_en = ~do_release_n & unpacker_ready;
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always @(posedge device_clk) begin
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if (mem_rd_en) begin
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mem_rd_data <= mem[rd_addr];
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end
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mem_rd_valid <= mem_rd_en;
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end
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always @(posedge device_clk) begin
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if (do_release_n) begin
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rd_addr <= 'b0;
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end else if (mem_rd_en) begin
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rd_addr <= rd_addr + 1;
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end
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end
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ad_upack #(
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.I_W(IWIDTH/8),
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.O_W(OWIDTH/8),
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.UNIT_W(8),
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.O_REG(0)
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) i_ad_upack (
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.clk(device_clk),
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.reset(do_release_n),
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.idata(mem_rd_data),
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.ivalid(mem_rd_valid),
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.iready(unpacker_ready),
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.odata(rd_data),
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.ovalid());
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end else begin
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if ((OWIDTH > IWIDTH) && ASYNC_CLK) begin
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ad_pack #(
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.I_W(IWIDTH/8),
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.O_W(OWIDTH/8),
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.UNIT_W(8)
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) i_ad_pack (
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.clk(clk),
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.reset(ready_n),
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.idata(wr_data),
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.ivalid(1'b1),
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.odata(mem_wr_data),
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.ovalid(mem_wr));
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end else begin
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assign mem_wr = 1'b1;
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assign mem_wr_data = wr_data;
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end
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always @(posedge clk) begin
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if (ready_n == 1'b1) begin
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wr_addr <= 'h00;
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end else if (mem_wr) begin
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mem[wr_addr] <= mem_wr_data;
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wr_addr <= wr_addr + 1'b1;
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end
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end
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always @(posedge device_clk) begin
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if (do_release_n == 1'b1) begin
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rd_addr <= 'h00;
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end else begin
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rd_addr <= rd_addr + 1'b1;
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mem_rd_data <= mem[rd_addr];
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end
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end
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assign rd_data = mem_rd_data;
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end
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endgenerate
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endmodule
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