315 lines
8.4 KiB
Verilog
Executable File
315 lines
8.4 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module jesd204_rx_lane #(
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parameter DATA_PATH_WIDTH = 4,
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parameter TPL_DATA_PATH_WIDTH = 4,
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parameter CHAR_INFO_REGISTERED = 0,
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parameter ALIGN_MUX_REGISTERED = 0,
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parameter SCRAMBLER_REGISTERED = 0,
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parameter ELASTIC_BUFFER_SIZE = 256,
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parameter ENABLE_FRAME_ALIGN_CHECK = 0,
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parameter ENABLE_CHAR_REPLACE = 0,
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parameter ASYNC_CLK = 0
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) (
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input clk,
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input reset,
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input device_clk,
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input device_reset,
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input [DATA_PATH_WIDTH*8-1:0] phy_data,
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input [DATA_PATH_WIDTH-1:0] phy_charisk,
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input [DATA_PATH_WIDTH-1:0] phy_notintable,
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input [DATA_PATH_WIDTH-1:0] phy_disperr,
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input cgs_reset,
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output cgs_ready,
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input ifs_reset,
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output [TPL_DATA_PATH_WIDTH*8-1:0] rx_data,
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output buffer_ready_n,
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input buffer_release_n,
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input [9:0] cfg_octets_per_multiframe,
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input [7:0] cfg_octets_per_frame,
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input cfg_disable_char_replacement,
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input cfg_disable_scrambler,
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output ilas_config_valid,
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output [1:0] ilas_config_addr,
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output [DATA_PATH_WIDTH*8-1:0] ilas_config_data,
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input err_statistics_reset,
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input [2:0] ctrl_err_statistics_mask,
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output reg [31:0] status_err_statistics_cnt,
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output [1:0] status_cgs_state,
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output status_ifs_ready,
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output [2:0] status_frame_align,
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output [7:0] status_frame_align_err_cnt
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);
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localparam MAX_DATA_PATH_WIDTH = 8;
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localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
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wire [7:0] char[0:DATA_PATH_WIDTH-1];
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wire [DATA_PATH_WIDTH-1:0] char_is_valid;
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reg [DATA_PATH_WIDTH-1:0] char_is_cgs = 1'b0; // K28.5 /K/
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reg [DATA_PATH_WIDTH-1:0] char_is_error = 1'b0;
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reg [DATA_PATH_WIDTH-1:0] charisk28 = 4'b0000;
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wire cgs_beat_is_cgs = &char_is_cgs;
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wire cgs_beat_has_error = |char_is_error;
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reg ifs_ready = 1'b0;
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reg [2:0] frame_align = 'h00;
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reg [2:0] frame_align_int;
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wire [DATA_PATH_WIDTH*8-1:0] phy_data_s;
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wire [DATA_PATH_WIDTH-1:0] charisk28_aligned_s;
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wire [DATA_PATH_WIDTH*8-1:0] data_aligned_s;
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wire [DATA_PATH_WIDTH-1:0] charisk28_aligned;
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wire [DATA_PATH_WIDTH*8-1:0] data_aligned;
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wire [DATA_PATH_WIDTH*8-1:0] data_replaced;
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wire [DATA_PATH_WIDTH*8-1:0] data_scrambled_s;
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wire [DATA_PATH_WIDTH*8-1:0] data_scrambled;
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reg [DATA_PATH_WIDTH-1:0] unexpected_char;
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reg [DATA_PATH_WIDTH-1:0] phy_char_err;
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wire ilas_monitor_reset_s;
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wire ilas_monitor_reset;
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wire buffer_ready_n_s;
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reg [DPW_LOG2:0] jj;
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reg align_found;
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assign status_ifs_ready = ifs_ready;
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assign status_frame_align = frame_align;
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genvar i;
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generate
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for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char
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assign char[i] = phy_data[i*8+7:i*8];
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assign char_is_valid[i] = ~(phy_notintable[i] | phy_disperr[i]);
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always @(*) begin
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char_is_error[i] = ~char_is_valid[i];
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char_is_cgs[i] = 1'b0;
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charisk28[i] = 1'b0;
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unexpected_char[i] = 1'b0;
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if (phy_charisk[i] == 1'b1 && char_is_valid[i] == 1'b1) begin
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if (char[i][4:0] == 'd28) begin
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charisk28[i] = 1'b1;
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if (char[i][7:5] == 'd5) begin
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char_is_cgs[i] = 1'b1;
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end
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end else begin
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unexpected_char[i] = 1'b1;
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end
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end
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end
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end
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endgenerate
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always @(posedge clk) begin
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if (cgs_ready == 1'b1) begin
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/*
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* Set the bit in phy_char_err if at least one of the monitored error
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* conditions has occured.
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*/
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phy_char_err <= (~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[0]}} & phy_disperr) |
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(~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[1]}} & phy_notintable) |
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(~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[2]}} & unexpected_char);
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end else begin
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phy_char_err <= {DATA_PATH_WIDTH{1'b0}};
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end
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end
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function [7:0] num_set_bits;
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input [DATA_PATH_WIDTH-1:0] x;
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integer j;
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begin
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num_set_bits = 0;
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for (j = 0; j < DATA_PATH_WIDTH; j = j + 1) begin
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num_set_bits = num_set_bits + x[j];
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end
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end
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endfunction
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always @(posedge clk) begin
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if (reset == 1'b1 || err_statistics_reset == 1'b1) begin
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status_err_statistics_cnt <= 32'h0;
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end else if (status_err_statistics_cnt[31:5] != 27'h7ffffff) begin
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status_err_statistics_cnt <= status_err_statistics_cnt + num_set_bits(phy_char_err);
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end
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end
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always @(posedge clk) begin
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if (ifs_reset == 1'b1) begin
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ifs_ready <= 1'b0;
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end else if (cgs_beat_is_cgs == 1'b0 && cgs_beat_has_error == 1'b0) begin
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ifs_ready <= 1'b1;
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end
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end
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always @(*) begin
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align_found = 1'b0;
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frame_align_int = 0;
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for(jj = 0; jj < DATA_PATH_WIDTH; jj=jj+1) begin
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if (!align_found && (char_is_cgs[jj] == 1'b0)) begin
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align_found = 1'b1;
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frame_align_int = jj;
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end
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end
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end
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always @(posedge clk) begin
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if (ifs_ready == 1'b0) begin
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frame_align <= frame_align_int;
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end
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end
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pipeline_stage #(
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.WIDTH(DATA_PATH_WIDTH*8),
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.REGISTERED(CHAR_INFO_REGISTERED)
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) i_pipeline_stage0 (
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.clk(clk),
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.in(phy_data),
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.out(phy_data_s));
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align_mux #(
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
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) i_align_mux (
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.clk(clk),
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.align(frame_align),
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.in_data(phy_data_s),
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.out_data(data_aligned_s),
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.in_charisk(charisk28),
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.out_charisk(charisk28_aligned_s));
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assign ilas_monitor_reset_s = ~ifs_ready;
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pipeline_stage #(
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.WIDTH(1 + DATA_PATH_WIDTH * (8 + 1)),
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.REGISTERED(ALIGN_MUX_REGISTERED)
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) i_pipeline_stage1 (
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.clk(clk),
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.in({
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ilas_monitor_reset_s,
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data_aligned_s,
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charisk28_aligned_s
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}),
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.out({
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ilas_monitor_reset,
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data_aligned,
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charisk28_aligned
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}));
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generate
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if (ENABLE_FRAME_ALIGN_CHECK) begin : gen_frame_align
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jesd204_rx_frame_align #(
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.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
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.ENABLE_CHAR_REPLACE (ENABLE_CHAR_REPLACE)
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) i_frame_align (
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.clk (clk),
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.reset (buffer_ready_n_s),
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.cfg_octets_per_multiframe (cfg_octets_per_multiframe),
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.cfg_octets_per_frame (cfg_octets_per_frame),
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.cfg_disable_char_replacement (cfg_disable_char_replacement),
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.cfg_disable_scrambler (cfg_disable_scrambler),
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.charisk28 (charisk28_aligned),
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.data (data_aligned),
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.data_replaced (data_replaced),
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.align_err_cnt (status_frame_align_err_cnt));
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end else begin : gen_no_frame_align_monitor
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assign status_frame_align_err_cnt = 32'd0;
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assign data_replaced = data_aligned;
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end
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endgenerate
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jesd204_scrambler #(
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.WIDTH(DATA_PATH_WIDTH*8),
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.DESCRAMBLE(1)
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) i_descrambler (
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.clk(clk),
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.reset(buffer_ready_n_s),
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.enable(~cfg_disable_scrambler),
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.data_in(data_replaced),
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.data_out(data_scrambled_s));
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pipeline_stage #(
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.WIDTH(1 + DATA_PATH_WIDTH * 8),
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.REGISTERED(SCRAMBLER_REGISTERED)
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) i_pipeline_stage2 (
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.clk(clk),
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.in({
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buffer_ready_n_s,
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data_scrambled_s
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}),
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.out({
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buffer_ready_n,
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data_scrambled
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}));
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elastic_buffer #(
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.IWIDTH(DATA_PATH_WIDTH*8),
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.OWIDTH(TPL_DATA_PATH_WIDTH*8),
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.SIZE(ELASTIC_BUFFER_SIZE),
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.ASYNC_CLK(ASYNC_CLK)
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) i_elastic_buffer (
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.clk(clk),
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.reset(reset),
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.device_clk(device_clk),
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.device_reset(device_reset),
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.wr_data(data_scrambled),
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.rd_data(rx_data),
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.ready_n(buffer_ready_n),
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.do_release_n(buffer_release_n));
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jesd204_ilas_monitor #(
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
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) i_ilas_monitor (
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.clk(clk),
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.reset(ilas_monitor_reset),
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.cfg_octets_per_multiframe(cfg_octets_per_multiframe),
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.data(data_aligned),
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.charisk28(charisk28_aligned),
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.data_ready_n(buffer_ready_n_s),
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.ilas_config_valid(ilas_config_valid),
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.ilas_config_addr(ilas_config_addr),
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.ilas_config_data(ilas_config_data));
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jesd204_rx_cgs #(
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
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) i_cgs (
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.clk(clk),
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.reset(cgs_reset),
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.char_is_cgs(char_is_cgs),
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.char_is_error(char_is_error),
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.ready(cgs_ready),
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.status_state(status_cgs_state));
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endmodule
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