70 lines
2.3 KiB
Verilog
70 lines
2.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module jesd204_tx_header (
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input clk,
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input reset,
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input [1:0] cfg_header_mode,
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input lmc_edge,
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input lmc_quarter_edge,
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// Header content to be sent must be valid during lmc_edge
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input eoemb,
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input [2:0] crc3,
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input [11:0] crc12,
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input [25:0] fec,
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input [18:0] cmd,
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output [1:0] header
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);
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reg header_bit;
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reg [31:0] sync_word = 'h0;
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always @(posedge clk) begin
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if (reset) begin
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sync_word <= 'h0;
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end else if (lmc_edge) begin
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case (cfg_header_mode)
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// CRC-12
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2'b00 : sync_word <= {crc12[11:9],1'b1,crc12[8:6],1'b1,
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crc12[5:3],1'b1,crc12[2:0],1'b1,
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cmd[6:4],1'b1,cmd[3],1'b1,eoemb,1'b1,
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cmd[2:0],5'b00001};
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// CRC-3
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2'b01 : sync_word <= { crc3[2:0],1'b1,cmd[6:4],1'b1,
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3'b000,1'b1,cmd[3:1],1'b1,
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3'b000,1'b1,cmd[0],1'b1,eoemb,1'b1,
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3'b000,5'b00001};
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// FEC
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2'b10 : sync_word <= { fec[25:18],
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fec[17:10],
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fec[9:4],eoemb,fec[3],
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fec[2:0],5'b00001};
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// Stand alone command
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2'b11 : sync_word <= { cmd[18:16],1'b1,cmd[15:13],1'b1,
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cmd[12:10],1'b1,cmd[9:7],1'b1,
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cmd[6:4],1'b1,cmd[3],1'b1,eoemb,1'b1,
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cmd[2:0],5'b00001};
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endcase
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end else begin
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if (lmc_quarter_edge && cfg_header_mode == 2'b01) begin
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sync_word <= {crc3[2],crc3[1],crc3[0],sync_word[27:0],1'b0};
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end else begin
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sync_word <= {sync_word[30:0],1'b0};
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end
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end
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end
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assign header = {~sync_word[31],sync_word[31]};
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endmodule
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