144 lines
3.8 KiB
Verilog
Executable File
144 lines
3.8 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module jesd204_tx_lane #(
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parameter DATA_PATH_WIDTH = 4,
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parameter ENABLE_CHAR_REPLACE = 1'b0
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) (
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input clk,
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input [DATA_PATH_WIDTH-1:0] eof,
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input [DATA_PATH_WIDTH-1:0] eomf,
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input cgs_enable,
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input [DATA_PATH_WIDTH*8-1:0] ilas_data,
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input [DATA_PATH_WIDTH-1:0] ilas_charisk,
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input [DATA_PATH_WIDTH*8-1:0] tx_data,
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input tx_ready,
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output reg [DATA_PATH_WIDTH*8-1:0] phy_data,
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output reg [DATA_PATH_WIDTH-1:0] phy_charisk,
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input [7:0] cfg_octets_per_frame,
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input cfg_disable_char_replacement,
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input cfg_disable_scrambler
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);
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wire [DATA_PATH_WIDTH*8-1:0] scrambled_data;
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wire [DATA_PATH_WIDTH*8-1:0] scrambled_data_d;
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wire cgs_enable_d;
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wire tx_ready_d;
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wire [DATA_PATH_WIDTH-1:0] eof_d;
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wire [DATA_PATH_WIDTH-1:0] eomf_d;
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wire [DATA_PATH_WIDTH*8-1:0] ilas_data_d;
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wire [DATA_PATH_WIDTH-1:0] ilas_charisk_d;
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wire [DATA_PATH_WIDTH*8-1:0] data_replaced;
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wire [DATA_PATH_WIDTH-1:0] charisk_replaced;
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wire [7:0] scrambled_char[0:DATA_PATH_WIDTH-1];
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reg [7:0] char_align[0:DATA_PATH_WIDTH-1];
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jesd204_scrambler #(
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.WIDTH (DATA_PATH_WIDTH*8),
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.DESCRAMBLE (0)
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) i_scrambler (
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.clk (clk),
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.reset (~tx_ready),
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.enable (~cfg_disable_scrambler),
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.data_in (tx_data),
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.data_out (scrambled_data));
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pipeline_stage #(
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.WIDTH ((DATA_PATH_WIDTH*19) + 2),
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.REGISTERED (1)
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) i_lane_pipeline_stage (
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.clk(clk),
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.in({
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cgs_enable,
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tx_ready,
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eof,
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eomf,
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scrambled_data,
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ilas_data,
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ilas_charisk
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}),
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.out({
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cgs_enable_d,
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tx_ready_d,
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eof_d,
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eomf_d,
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scrambled_data_d,
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ilas_data_d,
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ilas_charisk_d
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}));
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jesd204_frame_align_replace #(
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.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
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.IS_RX (1'b0),
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.ENABLED (ENABLE_CHAR_REPLACE)
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) i_align_replace (
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.clk (clk),
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.reset (~tx_ready_d),
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.cfg_octets_per_frame (cfg_octets_per_frame),
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.cfg_disable_char_replacement (cfg_disable_char_replacement),
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.cfg_disable_scrambler (cfg_disable_scrambler),
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.data (scrambled_data_d),
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.eof (eof_d),
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.rx_char_is_a ({DATA_PATH_WIDTH{1'b0}}),
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.rx_char_is_f ({DATA_PATH_WIDTH{1'b0}}),
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.tx_eomf (eomf_d),
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.data_out (data_replaced),
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.charisk_out (charisk_replaced));
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generate
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genvar i;
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for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char
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assign scrambled_char[i] = scrambled_data_d[i*8+7:i*8];
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always @(*) begin
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if (eomf_d[i]) begin
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char_align[i] = 8'h7c; // /A/
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end else begin
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char_align[i] = 8'hfc; // /F/
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end
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end
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always @(posedge clk) begin
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if (cgs_enable_d) begin
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phy_charisk[i] <= 1'b1;
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end else if (tx_ready_d) begin
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if(!cfg_disable_scrambler) begin
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phy_charisk[i] <= eof_d[i] && (scrambled_char[i] == char_align[i]);
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end else begin
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phy_charisk[i] <= charisk_replaced[i];
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end
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end else begin
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phy_charisk[i] <= ilas_charisk_d[i];
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end
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end
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end
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endgenerate
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always @(posedge clk) begin
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if (cgs_enable_d) begin
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phy_data <= {DATA_PATH_WIDTH{8'hbc}};
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end else begin
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if(tx_ready_d) begin
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phy_data <= data_replaced;
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end else begin
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phy_data <= ilas_data_d;
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end
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end
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end
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endmodule
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