67 lines
1.7 KiB
Verilog
67 lines
1.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module crc12_tb;
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parameter VCD_FILE = "crc12_tb.vcd";
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`define TIMEOUT 400
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`include "tb_base.v"
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reg [63:0] data_in = 'h0;
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reg [11:0] ref_crc12 = 'h0;
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wire [11:0] crc12;
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reg test_en = 1'b1;
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reg init = 1'b0;
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jesd204_crc12 DUT (
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.clk (clk),
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.reset (1'b0),
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.init (init),
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.data_in (data_in),
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.crc12 (crc12));
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// Test against dataset from the standard
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// - Test contiguous input stream with init phase
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initial begin
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@(negedge reset);
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@(posedge clk);
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repeat (3) begin
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@(posedge clk) data_in <= 'h80_01_02_03_05_05_04_23;
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init <= 1'b1;
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@(posedge clk) data_in <= 'h0e_43_80_c2_0b_50_81_cd;
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init <= 1'b0;
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@(posedge clk) data_in <= 'h04_e7_83_92_5a_3c_aa_51;
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@(posedge clk) data_in <= 'h05_4d_87_d9_31_3d_11_51;
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end
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@(posedge clk);
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@(posedge clk);
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test_en <= 1'b0;
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end
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initial begin
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@(negedge reset);
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@(posedge clk);
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@(posedge clk);
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repeat(3) begin
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@(posedge clk) ref_crc12 <= 'hd00;
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@(posedge clk) ref_crc12 <= 'h11c;
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@(posedge clk) ref_crc12 <= 'hfea;
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@(posedge clk) ref_crc12 <= 'h5fe;
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end
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end
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always @(posedge clk) begin
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if (ref_crc12 != crc12 && failed == 1'b0 && test_en) begin
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failed <= 1'b1;
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end
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end
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endmodule
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