40 lines
1.4 KiB
Verilog
Executable File
40 lines
1.4 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module jesd204_frame_mark_tb;
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parameter VCD_FILE = "jesd204_frame_mark_tb.vcd";
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`define TIMEOUT 1000000
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`include "tb_base.v"
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localparam DATA_PATH_WIDTH = 8;
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wire [9:0] cfg_octets_per_multiframe = 23;
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wire [7:0] cfg_beats_per_multiframe = 2;
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wire [7:0] cfg_octets_per_frame = 5;
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wire [DATA_PATH_WIDTH-1:0] sof;
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wire [DATA_PATH_WIDTH-1:0] somf;
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wire [DATA_PATH_WIDTH-1:0] eof;
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wire [DATA_PATH_WIDTH-1:0] eomf;
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jesd204_frame_mark #(
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.DATA_PATH_WIDTH (DATA_PATH_WIDTH)
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) frame_mark (
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.clk (clk),
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.reset (reset),
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.cfg_octets_per_multiframe (cfg_octets_per_multiframe),
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.cfg_beats_per_multiframe (cfg_beats_per_multiframe),
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.cfg_octets_per_frame (cfg_octets_per_frame),
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.sof (sof),
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.eof (eof),
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.somf (somf),
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.eomf (eomf));
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endmodule
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