58 lines
1.4 KiB
Verilog
58 lines
1.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module rx_cgs_tb;
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parameter VCD_FILE = "rx_cgs_tb.vcd";
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`define TIMEOUT 1000
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`include "tb_base.v"
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reg [3:0] char_is_error = 4'b0000;
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reg [3:0] char_is_cgs = 4'b1111;
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integer counter = 'h00;
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wire ready;
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reg ready_prev = 1'b0;
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/*
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always @(posedge clk) begin
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if ($random % 2 == 0)
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char_is_error <= 4'b1111;
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else
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char_is_error <= 4'b0000;
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end
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*/
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always @(posedge clk) begin
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counter <= counter + 1;
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if (counter == 'h20) begin
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char_is_cgs <= 4'b0001;
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end else if (counter > 'h20) begin
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char_is_cgs <= 4'b0000;
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end
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end
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jesd204_rx_cgs i_rx_cgs (
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.clk(clk),
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.reset(reset),
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.char_is_cgs(char_is_cgs),
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.char_is_error(char_is_error),
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.ready(ready));
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reg lost_sync = 1'b0;
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always @(posedge clk) begin
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ready_prev <= ready;
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if (ready_prev == 1'b1 && ready == 1'b0) begin
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lost_sync <= 1'b1;
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end
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failed <= lost_sync | ~ready;
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end
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endmodule
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