76 lines
1.9 KiB
Verilog
76 lines
1.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module rx_ctrl_tb;
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parameter VCD_FILE = "rx_ctrl_tb.vcd";
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`include "tb_base.v"
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integer phy_reset_counter = 'h00;
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integer align_counter = 'h00;
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integer cgs_counter = 'h00;
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reg phy_ready = 1'b0;
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reg aligned = 1'b0;
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reg cgs_ready = 1'b0;
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wire en_align;
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wire cgs_reset;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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phy_reset_counter <= 'h00;
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phy_ready <= 1'b0;
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end else begin
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if (phy_reset_counter == 'h7) begin
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phy_ready <= 1'b1;
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end else begin
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phy_reset_counter <= phy_reset_counter + 1'b1;
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end
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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aligned <= 1'b0;
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align_counter <= 'h00;
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end else if (phy_ready == 1'b1) begin
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if (en_align == 1'b1) begin
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if (align_counter == 'h20) begin
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aligned <= 1'b1;
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end else begin
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align_counter <= align_counter + 1;
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end
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end
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end
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end
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always @(posedge clk or posedge cgs_reset) begin
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if (cgs_reset == 1'b1) begin
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cgs_counter <= 'h00;
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cgs_ready <= 1'b0;
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end else begin
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if (cgs_counter == 'h20) begin
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cgs_ready <= 1'b1;
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end else begin
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cgs_counter <= cgs_counter + 1;
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end
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end
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end
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jesd204_rx_ctrl i_rx_ctrl (
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.clk(clk),
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.reset(reset),
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.phy_ready(phy_ready),
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.phy_en_char_align(en_align),
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.cgs_reset(cgs_reset),
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.cgs_ready(cgs_ready));
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endmodule
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