105 lines
2.8 KiB
Verilog
105 lines
2.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module scrambler_64b_tb;
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parameter VCD_FILE = "scrambler_64b_tb.vcd";
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`include "tb_base.v"
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reg failed_t1 = 1'b0;
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reg failed_t2 = 1'b0;
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// Test scrambler against descrambler
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//
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// Descrambled data should match the input of the scrambler.
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reg [63:0] data_in = 'h0;
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reg [63:0] data_out_expected;
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wire [63:0] data_scrambled;
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wire [63:0] data_out;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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data_in <= 'h0001020304050607;
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end else begin
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data_in <= data_in + {8{8'h08}};
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end
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end
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jesd204_scrambler_64b #(
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.DESCRAMBLE(0)
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) i_scrambler (
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.clk(clk),
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.reset(reset),
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.enable(1'b1),
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.data_in(data_in),
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.data_out(data_scrambled));
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jesd204_scrambler_64b #(
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.DESCRAMBLE(1)
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) i_descrambler (
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.clk(clk),
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.reset(reset),
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.enable(1'b1),
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.data_in(data_scrambled),
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.data_out(data_out));
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always @(posedge clk) begin
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if (data_in != data_out && failed_t1 == 1'b0) begin
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failed_t1 <= 1'b1;
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end
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end
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// Test descrambler against reference data
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//
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// Check if descrambler can synchronize and a stream captured from
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// a scrambler output. The descrambled data stream should match the input of
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// the scrambler.
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reg [63:0] descrambler_data_in = 'h0;
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reg [63:0] data_ref = 'h0;
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wire[63:0] descrambler_data_out;
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integer i;
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reg [63:0] scrambler_64b_input [0:993];
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reg [63:0] scrambler_64b_output [0:993];
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reg t2_enable = 1'b0;
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initial begin
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$readmemh("scrambler_64b_input.txt", scrambler_64b_input); // Input to a scrambler
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$readmemh("scrambler_64b_output.txt", scrambler_64b_output); // Output of a scrambler
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@(negedge reset);
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@(posedge clk);
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for (i=0;i<994;i=i+1) begin
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@(posedge clk);
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descrambler_data_in <= scrambler_64b_output[i];
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data_ref <= scrambler_64b_input[i];
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if (i==1) t2_enable <= 1'b1;
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if (i==993) t2_enable <= 1'b0;
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end
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end
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jesd204_scrambler_64b #(
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.DESCRAMBLE(1)
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) i_descrambler2 (
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.clk(clk),
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.reset(reset),
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.enable(1'b1),
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.data_in(descrambler_data_in),
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.data_out(descrambler_data_out));
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always @(posedge clk) begin
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if (data_ref != descrambler_data_out && failed_t2 == 1'b0 && t2_enable) begin
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failed_t2 <= 1'b1;
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end
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end
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always @(posedge clk) begin
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failed <= failed_t1 || failed_t2;
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end
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endmodule
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